TMS320F280049: How does SYSCLK and ADCCLK impact ADC sampling, conversion, and result?

Hi Wayne,

S+H duration needs to be increased from the minimum if the input impedance is higher than ideal or the driving BW is lower than ideal. Ideal would be in the ballpark of around a 10MHz+ op-amp driving a 50 ohm or less purely resistive input. Increased S+H duration will result in increased trigger-to-output latency and reduced sample-rate if samples are back-to-back.

Reducing the ADCCLK will result in the conversions taking longer, so trigger-to-output latency, sample-to-output latency, and time to sample back-to-back conversions will all increase.

Usually you want to run at the maximum possible ADCCLK to reduce latency. There is no power savings from reducing the ADCCLK since the clock does not free-run when not being used for conversions.

The main reason to be able to adjust the ADCCLK PRESCALE would be if a different SYSCLK is used, a different divider is needed get max or as close to possible to max ADCCLK.

If a VREFHI driving circuit is used that doesn't have very good BW and/or the capacitor between VREFHI and VREFLO is too small or is placed too far from the reference pins then the ADC may not be able to operate at its maximum rated frequency. In this case, it may be necessary to reduce the ADCCLK to mitigate the effects of poor reference design.