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TMS320F28377D: ADC conversion depend of value on other channel! ??

A GIR
Genius 3615 points

Part Number: TMS320F28377D
Other Parts Discussed in Thread: OPA320

Hello

We are developing a BLDC board.

To do this, we use the 28377 controller.

We use the ADC to get the DCLink voltage (about 24VDC) and then the motor phase current (U and V).

The DCLink voltage is divided by resistor ( divisor = 21).

The Phase current is getting by a shunt resistor of 8mohms and then amplificator.

An extract of the scheme is provided.

The current measure is Ok.

The DCLink voltage is Ok.

But now, we control the motor. All run correctly.

Now, on a speed Loop control, we asked null speed. Then motor not turn, but a torque is applied. Then when we try to move the motor with the hand, the measured motor current increase proportinally to the torque applied.

Until now, all it is Ok!

But on this state (Motor speed = 0 with an hand applied torque), the ADC measure done on the channel affected to the DCLink increase whereas ADC input stay stable! Then the software get about 30V whereas the input represent 24V!

The current in phase motor is 4A. This correspond to the ADC get value.

It is like the ADC input of the Motor phase current affect the measured value on the channel for the DCLink voltage!

I check all other voltage (GND, VRef HI, Vref Low etc..) All physical voltage is Ok.

Just the register AdccResultRegs.ADCRESULT1 increase from #1390 to about #1500...#1600 !

The Analog input of the DCLink is 1.13V, this correspond to the 24V of the DCLink. #1500..#1600 should say this input is about 25..26V.

This error increase with motor current. When motor current is about 10A, the Measure DCLink up to 30V whereas Physical DClink voltage stay to 24V...

Schema:

This is the Init code :

  /* *********************************/
  /* Resolver Fbk - sine             *//* NOTE!!! ADCINC2 not used on this board, linked to GND */
  /* *********************************/
  AdccRegs.ADCSOC0CTL.bit.CHSEL     = 2;     /* Configure the Pin associated to the Adc/SOC */
  AdccRegs.ADCSOC0CTL.bit.ACQPS     = 30;                           /* sample window in SYSCLK cycles (ACQPS + 1) x 200MHz ^-1 = 155ns (Datasheet min = 75ns) */
  AdccRegs.ADCSOC0CTL.bit.TRIGSEL   = 15;   /* PWM6 SocA => 160KHz */ /* Selection on which event Soc will trig the start of conversion */


  /* ***************************************/
  /* Bus Voltage Feedback                  */
  /* ***************************************/
  AdccRegs.ADCSOC1CTL.bit.CHSEL     = 3;         /* Configure the Pin associated to the Adc/SOC */
  AdccRegs.ADCSOC1CTL.bit.ACQPS     = 30;        /* sample window in SYSCLK cycles (ACQPS + 1) x 200MHz ^-1 = 155ns (Datasheet min = 75ns) */
  AdccRegs.ADCSOC1CTL.bit.TRIGSEL   = 5;         /* PWM1 SocA => 10KHz *//* Selection on which event Soc will trig the start of conversion */

    /* ****************************/
    /* Shunt motor current V         */
    /* *********************************/

    AdcdRegs.ADCSOC0CTL.bit.CHSEL     = 3;     /* Configure the Pin associated to the Adc/SOC */
    AdcdRegs.ADCSOC0CTL.bit.ACQPS     = 30;    /* sample window in SYSCLK cycles (ACQPS + 1) x 200MHz ^-1 = 155ns (Datasheet min = 75ns) */
    AdcdRegs.ADCSOC0CTL.bit.TRIGSEL   = 5;     /* PWM1 SocA => 10KHz *//* Selection on which event Soc will trig the start of conversion */

    /* Configure PPB to eliminate subtraction related calculation                                        */
    AdcdRegs.ADCPPB1CONFIG.bit.CONFIG = 0;     /* PPB is associated with SOC0 */
    AdcdRegs.ADCPPB1CONFIG.bit.OFFCAL = 0;     /* Write zero to this for now till offset ISR is run     */

What could be the cause of the "ADC dependence"?

  • 0
    TI__Guru 60865 points

    Hi A GIR,

    Is the 'U' phase sampled?  

    Usually if one signal is affecting another it is (1) on the same ADC and (2) because of too high of input impedance and/or too short of S+H duration.  The easiest test for this is to really increase ACQPS to some large value (max is 511) to see if the problem is eliminated or reduced.  You can also sample the internal VREFLO connection right before sampling your channel which, if this helps, would also indicate the same issue of high input impedance/too short S+H duration.  

    What exactly is on the VREFHI inputs?  Is the 100 ohms in series with 10uF?  You need the R to be in the ballpark of  ~1 ohm or less.  The series resistor is there to ensure the driving op-amp is stable, but the driving op-amp needs to be very good at driving capacitive loads (OPA320 is recommended in the device documentation).  You might try reducing this R (assuming the op-amp will remain stable).  You can reduce the C if necessary down to maybe 1uF.  You may also want to try turning the ADCCLK down significantly with this reference circuit; maybe set the PRESCALE to /8?  This will give you 25MHz  ADCCLK.  You would need to reduce the SYSCLK to reduce ADCCLK further.

    To ensure that SOCs on different ADCs occur in parallel, you might want to add a dummy conversion on ADC-D and line up the SOCs such that ADC-C and ADC-D SOCx use the same trigger source and S+H duration for a given x and that if a given x exists on one ADC it also is used on the other (possibly just sampling a dummy channel/internal VREFLO connection).  



  • 0 in reply to Devin Cottier
    Genius 3615 points

    Hi,

    - The Phase U is sampled like phase V but on ADCA3.

    - Like schematic indicate, the VREFH has the C + R like in the Demonstration board.

    - I try to increase ACQPS but without success.

    But I check the needed sample time. Effectively, I configured the register to 30 (205ns) whereas the DC Link is generated from a resistor bridge (165K / 8.2K) then with a ADC input capacity of 14pF the nees is about 1 to 1.2µs!.

    But like said above, I try to configure for 1.5µs without change.

    Then I change the resistor bridge value (10K /500 ohms), With this, the sample time could be 100ns. And then, after try, the measure is ok now.

    Thank for your help