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TMS320F28374S: Design support

Yash Dave
Intellectual 620 points

Part Number: TMS320F28374S
Other Parts Discussed in Thread: LAUNCHXL-F28379D

HI,

As per datasheet, there should be Capacitor between VREFHIA and VREFLOA pins.  (datasheet page no. 18)

I checked reference schematic of launchpad. It is directly connected in launchpad. Can you advise correct way for 12-bit mode.?

  • 0
    TI__Guru* 84570 points
    Yash,

    Thanks for reaching out, the schematic for the F28379D(page7) is a bit misleading, as the circuitry that drives the VREFHI pins is on another page.

    This is on page 3, and there is a 22uF cap(to support 16 bit mode) between the respective VREFHIs and VSS. In this case, since VREFLO is hard tied to VSS we are meeting the requirement in the DS on the LP.

    Best,
    Matthew
  • 0 in reply to MatthewPate
    Prodigy 80 points
    Part Number: TMS320F28374S

    Need someone urgently to review a general schematic for TMS320F28374S.

    My mail ID:development@sydlerelectro.com

    Please guide me where to send or post.

    Thanks and regards

    Nikhil
  • 0 in reply to nik wag
    TI__Guru* 84570 points

    Nikhil,

    Is this related to Yash's inquiry or a different request?  Depending on your answer I'll continue here are re-activate one of the other threads you created.

    In general the E2E can be used to address technical questions on the usage or implementation of a TI device(in this case C2000 MCU).  If that dialogue leads to a portion of the schematic that needs to be looked at the C2000 community can support that. 

    For a complete schematic review of your design I would recommend reaching out to your local sales or distribution representative for assistance.

    Again, any specific C2000 MCU question can be answered here, but we prefer that to be handled on the forum itself(vs direct email), so that the findings can be beneficial to the E2E community.

    Best,

    Matt

  • 0 in reply to MatthewPate
    Prodigy 80 points

    Yes, It is related to Yash's enquiry. I have prepared a schematic for TMS320F28347S. It is just like a generalised development board/testing board with all the i/o's placed on a connector [Just like a launch pad board]. I need someone to review its major connections like the VDDIO/VDD/VDDOSC/VSSA/etc. supply voltages and JTAG connection.

    Also it will be helpful to the entire E2E community since it will be a proven and tested design.

    Thanks and Regards

    Nikhil

  • 0 in reply to nik wag
    TI__Guru* 84570 points
    Nikhil,
    Using the LP as a initial target for general connections as you mention is the right way to go. If you want to post either the schematic or images of the sections of the schematic you want looked at, please do so to this thread.

    Best,
    Matthew
  • 0 in reply to MatthewPate
    Prodigy 80 points

    Dear Mr. Mathew,

    Please find the document attached below.

    ControlCard.docx

  • 0 in reply to nik wag
    TI__Guru* 84570 points

    Nik,

    I'd like to make sure you have cross checked this design with the F28379D LP  http://www.ti.com/tool/launchxl-f28379d, I think will rectify most of the concerns I have:

    1)I do not see a 1.2V rail for the VDD pins.  This is the core voltage of the device, and currently is tied to 3.3V.  You can see the voltage regulator we used on the LP in the BOM/schematics posted above.

    2)There are several places there are jumpers to tie GPIOs for a "1" or "0", however the listed voltage is 5V.  Recall that this (and most all) C2000 MCUs are 3.3V VDDIO rail devices.  There is already 3.3V rail you have generated for VDDIO on the board, so this should be straightforward.

    3)The VDDIO rail has alot of decoupling capacitance, 100uF on each pin with a 2200uF main cap.  Again, I would look at the LP schematics, where there is a few 10uF caps and local 100nF(at the pin) caps.  For VDD we have a little more cap, 2.2uF at each pin.  #1 above still needs to be corrected

    4)VREFHI is being derived from a potentiometer, this will likely not give enough accuracy/stability to maintain the DS numbers for the ADC, especially if you want to do 16-bit level conversions.  Again, I would refer back to the LP implemenation for a known good model with an external reference.  If nothing else you must change the capacitance value and type to match the LP or DS recommendations.

    5)You should consider adding a switch to the XRSn signal net.  While not an absolute it will allow a way to manually recover the device from a unknown state,

    Best,
    Matthew

  • 0 in reply to MatthewPate
    Prodigy 80 points

    Please refer attached modified schematic as suggested.

    I think it is complete now. will update when i will test the same.

    Please share with everybody in need.

    Regards

    Nikhil3058.ControlCard.docx

  • 0 in reply to nik wag
    TI__Guru* 84570 points
    Nik,
    On page 2 I would remove C11s, the 2.2uF cap between VSSA and VSS as well as the R7 shunt and just tie VSSA to VSS directly. This should help simplify the layout as well.

    On page 3 I would recommend replacing C52 with a ceramic cap of 22uF. My biggest concern is the VREFHI circuit in general; this will not be very accurate nor well driven, esp for 16-bit ADC resolution. I would highly recommend replicating the circuit in either the LAUNCHXL-F28379D or the TMDSF28379DCNCD for VREFHI.

    Everything else looks OK to me.

    Best,
    Matthew
  • 0 in reply to MatthewPate
    Prodigy 80 points
    Yes, there was a mistake with the VSSA pins. i have removed the caps.
    i will change C52 with 22uF ceramic cap.
    For the VREFHI pins i will be using only 12-bit adc, and if required i will change the circuit in next design. but as of now i will use the same design.

    Thank you so much for the help.

    Regards
    nikhil