Piccolo CLA: Branch instructions

Martin Rosenau said:

In the Piccolo CLA manual it is said that two branch instructions must be 3 instructions "away" from one another:

MBCNDD x1,LEQ
MNOP
MNOP
MNOP
MBCNDD x2,GT

Is this a real requirement (MIPS or SPARC processors would cause a TRAP if a jump instruction is found in the delay slot) or just a pseudo-requirement to avoid unexpected behaviour?

This is a real requirement. 

-Lori

hi,

ya this is a real requirement because flags that will affect jump condition are computed first and they actual jump occurs so it necessary 

This is what I do not understand.

I thaught the CLA would work the following way:

1. MCMPF32 MR0,#1.0
2. MCMPF32 MR0,#2.0
3. <any instruction, not branch/call/stop/return>
4. <any instruction, not branch/call/stop/return>
5. MBCNDD case_1, EQ
6. MBCNDD case_2, EQ

The decision if the branch #5 is taken is done after executing instruction #1.
Therefore instruction #2 will not affect the branch #5 and lines 1-5 would work propperly (branch #5 occurs depending on instruction #1 result).

Due to the pipeline timing instruction #2 will affect a branch in position #6 (if #5 was not a branch).
The conditions from instruction #1 and instruction #2 cannot be both true.
If the branch #5 is taken - so I thaught - the conditions for branch #6 will be false so the processor treats #6 like a NOP (branch not taken).
It the branch #5 is not taken - so my idea - instruction #5 is treated like a NOP (branch not taken) and #6 can be a branch...

So my actual question should be:
Do I need "MNOP" instructions between conditional branches even if I can ensure that only one branch condition is true and the other branches are not taken?

I know that other processor architectures (MIPS, SPARC) would explicitly fail with a trap interrupt in this case so it is not possible to do this with such processors.

Martin

hi,

if i can know more about your algorithm i can help you with that as well

but just one point that iwant o mention

1.Three instruction after branch/call/return will be executed no matter branch is taken or not

so if we put this to your case then there are two possibilities

1.if branch is taken then your next branch istruction will also execute and may overite the PC(if thereis no check in hardware to prevent it) so it depend on your second branch

2.if first one is not taken it will work

so it will behave unexpectidly

here is one explanation

<Instruction 1> ; I1 Last instruction that can affect flags for the branch, call or return operation

<Instruction 2> ; I2 Cannot be stop, branch, call or return

<Instruction 3> ; I3 Cannot be stop, branch, call or return

<Instruction 4> ; I4 Cannot be stop, branch, call or return

<branch/call/ret> ; MBCNDD, MCCNDD or MRCNDD

; I5-I7: Three instructions after are always executed whether the branch/call or return is taken or not

<Instruction 5> ; I5 Cannot be stop, branch, call or return

<Instruction 6> ; I6 Cannot be stop, branch, call or return

<Instruction 7> ; I7 Cannot be stop, branch, call or return

<Instruction 8> ; I8

<Instruction 9> ; I9

check document  "SPRUGE6B" Page 34 Example 1

i hope its awnser ,also give your feedback