Team,
My customer is looking for clarification on layout for F28379D:
I’ve designed in a TMS320F28379D Delfino CPU and we are beginning to work on board layout.
We have some questions regarding the footprint design.
The datasheet appears to call for a large copper pad and a via field under most of the package as shown below.
However, when we downloaded the TI pre-built footprint for Allegro, we noticed it has no via field and the pad is much smaller.
There are also some slight differences in the size of the pads for the leads.
We want to be sure we have the best footprint design possible, and that we provide sufficient thermal vias.
Our board is at least 4 layers with a ground plane to connect to the thermal pad.
What does TI recommend for this part?
Thanks
Viktorija