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TMS320F28379D: footprint design question

Part Number: TMS320F28379D


Team,

My customer is looking for clarification on layout for F28379D:

I’ve designed in a TMS320F28379D Delfino CPU and we are beginning to work on board layout.

We have some questions regarding the footprint design.

The datasheet appears to call for a large copper pad and a via field under most of the package as shown below.

However, when we downloaded the TI pre-built footprint for Allegro, we noticed it has no via field and the pad is much smaller.

There are also some slight differences in the size of the pads for the leads.

 

We want to be sure we have the best footprint design possible, and that we provide sufficient thermal vias.

Our board is at least 4 layers with a ground plane to connect to the thermal pad.

What does TI recommend for this part?

Thanks

Viktorija

  • 7041.hwg_16c.zipViktorija,

    I have contacted a footprint specialist for this device. In the mean time please take a look at the attached document. It explains the use of thermal pads/vias and choices/trade-offs that can be used.

    Regards,

    PEter

  • Vikrorija,

    The bxl actually includes three IPC variations of the footprint, which explains why there are different pad sizes between footprints. The PTP0176F drawing in the datasheet is the optimal footprint for them to use according to TI, and the PTP0176F_N footprint in the bxl is essentially the same as the drawing.

    If there are no vias and a much smaller thermal pad in the Allegro footprint, there may be a problem with the Cadence translation.

    Regards,
    PEter