TMS320F28377S: QEP Reset counter on Index Event

A GIR

Genius 3615 points

Part Number: TMS320F28377S

Hello,

I'm using an F28337 to control a BLDC motor with QEP feedback.

The QEP Hw is configured to Reset the counter on Index Event?

Like the TI exemple IDDK, We have a Timer Interrupt every 100µs.

In it, we check the flag QFLG.IEL

On the fisrt start, the QEP counter cross the Index event at any hasardous value (depending of the motor position at power on)

Then this value is latched to the QPOSILAT and counter should be set to 0 or QPOSMAX.

But on 100µs interrupt, when I get the IEL flag to 1, I get the counter value. I'm expecting this value is near to 0 or QPOSMax (according motor distance run between the Hardware Index event and the 100µs interrupt.)

But it is not the case, the Counter value is always near to the value when Topz is crossed (then near QPOSILAT).

Why, when I get the IEL flag set, the CNT is not yet Reset?

over 8 years ago

0 Mark Labbato over 8 years ago

Guru 30330 points

Hi there,

Refer to the section "Position counter Reset on Index Event (QEPCTL[PCRM]=00) for how to set up the Position Counter to reset on n index event.

It sounds like you are just latching the current position counter value into the QPOSILAT on the index event.

What is the current setting of QEPTCL.PCRM? Ensure that it is set to 00.

0 A GIR over 8 years ago in reply to Mark Labbato

Genius 3615 points

Hello

The QEPCTL[PCRM] = 0 => Reset on Index event.

I monitored the QEP signal. I haven't Index event. Only A and B signal.

In fact, It is like my manual CNT assignation haven't effect.

I read on this forum this register should be consider as Read only when QEP is running. Then I try to Set QPEN = 0, Set CNT= XXXX(Depending of Hall sensor position) and then QPEN = 1.

But half time, the counter was not set by this procedure.

Then I made the Following test:

My code call these code:

/*-----------------------------------------------------------------------------
    Initialization states for EQEP Decode Control Register
------------------------------------------------------------------------------*/
#define DV_QEP_QDECCTL_INIT_STATE     ( XCR_X2 + QSRC_QUAD_MODE )

/*-----------------------------------------------------------------------------
    Initialization states for EQEP Control Register
------------------------------------------------------------------------------*/
#define DV_QEP_QEPCTL_INIT_STATE      ( QEP_EMULATION_FREE + \
                                        PCRM_INDEX + \
                                        0 + \
                                        IEL_RISING + \
                                        QPEN_ENABLE + \
                                        QCLM_TIME_OUT + \
                                        UTE_DISABLE )
/*-----------------------------------------------------------------------------
    Initialization states for EQEP Position-Compare Control Register
------------------------------------------------------------------------------*/
#define DV_QEP_QPOSCTL_INIT_STATE      PCE_DISABLE

/*-----------------------------------------------------------------------------
    Initialization states for EQEP Capture Control Register
------------------------------------------------------------------------------*/
#define DV_QEP_QCAPCTL_INIT_STATE     ( UPPS_X32 + \
                                        CCPS_X128 + \
                                        CEN_ENABLE )

  /* Setup GPIO for QEP operation */                                                                              \
  GPIO_SetupPinOptions(DV_Qep_PinCfg[m][PinSet].QepPinA , GPIO_INPUT, GPIO_SYNC);    /* QEP1A */                  \
  GPIO_SetupPinMux(DV_Qep_PinCfg[m][PinSet].QepPinA , GPIO_MUX_CPU1, DV_Qep_PinCfg[m][PinSet].GpioMux );          \
  GPIO_SetupPinOptions(DV_Qep_PinCfg[m][PinSet].QepPinB , GPIO_INPUT, GPIO_SYNC);    /* QEP1B */                  \
  GPIO_SetupPinMux(DV_Qep_PinCfg[m][PinSet].QepPinB , GPIO_MUX_CPU1, DV_Qep_PinCfg[m][PinSet].GpioMux);           \
  /*GPIO_SetupPinOptions(DV_Qep_PinCfg[m][PinSet].QepPinS , GPIO_INPUT, GPIO_SYNC);*/    /* QEP1S ???*/           \
  /*GPIO_SetupPinMux(DV_Qep_PinCfg[m][PinSet].QepPinS , GPIO_MUX_CPU1, DV_Qep_PinCfg[m][PinSet].GpioMux);*/       \
  GPIO_SetupPinOptions(DV_Qep_PinCfg[m][PinSet].QepPinI , GPIO_INPUT, GPIO_SYNC);    /* QEP1I */                  \
  GPIO_SetupPinMux(DV_Qep_PinCfg[m][PinSet].QepPinI , GPIO_MUX_CPU1, DV_Qep_PinCfg[m][PinSet].GpioMux);           \
                                                                                                                  \
  /* Reset Hw module */                                                                                           \
  switch (m)                                                                                                      \
  {                                                                                                               \
    case 1:                                                                                                       \
      DevCfgRegs.SOFTPRES4.bit.EQEP1 = 1;                                                                         \
      DevCfgRegs.SOFTPRES4.bit.EQEP1 = 0;                                                                         \
      break;                                                                                                      \
    case 2:                                                                                                       \
      DevCfgRegs.SOFTPRES4.bit.EQEP2 = 1;                                                                         \
      DevCfgRegs.SOFTPRES4.bit.EQEP2 = 0;                                                                         \
      break;                                                                                                      \
    case 3:                                                                                                       \
      DevCfgRegs.SOFTPRES4.bit.EQEP3 = 1;                                                                         \
      DevCfgRegs.SOFTPRES4.bit.EQEP3 = 0;                                                                         \
      break;                                                                                                      \
  }                                                                                                               \
                                                                                                                  \
  (*DV_Qep_Regs[m]).QDECCTL.all  = DV_QEP_QDECCTL_INIT_STATE;                                                     \
  (*DV_Qep_Regs[m]).QPOSCTL.all  = DV_QEP_QPOSCTL_INIT_STATE;                                                     \
  (*DV_Qep_Regs[m]).QUPRD        = 0;             /* Unit Timer for 100Hz*/                                       \
  (*DV_Qep_Regs[m]).QCAPCTL.all  = DV_QEP_QCAPCTL_INIT_STATE;                                                     \
  (*DV_Qep_Regs[m]).QPOSMAX      = (4 * v.LineEncoder) - 1;                                                       \
  (*DV_Qep_Regs[m]).QEPCTL.all   = 0;                   /* By setting to 0 and Enable, reset the HW QEP */        \
  (*DV_Qep_Regs[m]).QEPCTL.all   = DV_QEP_QEPCTL_INIT_STATE;                                                      \

((*DV_Qep_Regs[m]).QPOSCNT = 2500);

((*DV_Qep_Regs[m]).QCLR.bit.IEL = 1)

After that, the JTAG is in "Pause". The CNT is 2500. By this way, I'm sure that have no part in my code which will be have a bad behavior. I let the Hardwar "alone"

Then I move the motor (only 1 or 2°). I monitor A, B and TopZ signal. A and B generate some Rising/Falling Edge. TopZ still always to 0.

But QEP CNT return to 0 and finish to 9892 which correspond to my case to a small move (From 9999 to 9892)...

The CNT has reset!...QFLG.IEL = 0...

0 A GIR over 8 years ago in reply to A GIR

Genius 3615 points

Hello
I forget to call EALLOW and then EDIS to have access to SOFTPRES4 register.
Now after that, the solution work properly.

To resume:
After Power On the QEP, the Hw QEP need softReset because a TopZ event is received on Hardware line.

0 Mark Labbato over 8 years ago in reply to A GIR

Guru 30330 points

Hi A GIR,

I am glad that you were able to figure out a solution to your issue. Please don't hesitate to post again in the future if you encounter any new issues.

-Mark

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TMS320F28377S: QEP Reset counter on Index Event