TMS320F28335: facing problem in McBSP module of TMS320F28335

i am using McBSP-b for serial commuincation(SPI) between TMS320F28335 and Intel FPGA.

Tms320F28335 is configured as master.

Currently I am transmitting & receiving 4 words of 32 bit  (128 bits) single phase data .

I am able to successfully transmit data 128bit data  from dsp to FPGA, and CRC of data generated from dsp is also matching at FPGA end.

But while receiving 128 bit data from FPGA either some of the packets are missed/ or it is not in correct order.

But the received data (128 bit) is same order as transmitted by FPGA and it is validated in CRO.

The program is working fine when configured for 32 bit data. There is no problem in transmission and receiption.

But when I increase the no. of words per phase, I am facing problem in received data.

Below are the mcbsp configuration and transmit & receive function. 

void init_mcbsp_spi()

{

       EALLOW;

       SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-A

       EDIS;

      

       McbspbRegs.SPCR2.all=0x0000;                    // Reset FS generator, Sample Rate Generator & Transmitter

       McbspbRegs.SPCR1.all=0x0000;                    // Reset Receiver, Right justify word, Digital loopback dis.

       //McbspaRegs.PCR.all=0x0F08;                    //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1) // need to check

       McbspbRegs.SPCR1.bit.DLB = 0;                   // Digital Loopback Mode

       // McBSP as SPI Master clock

       McbspbRegs.SPCR1.bit.CLKSTP = 2;                // Together with CLKXP/CLKRP determines clocking scheme

       McbspbRegs.PCR.bit.CLKXP = 0;                   // MCLKX pin polarity: Rising edge on MCLKX pin generates transitions on CLKG & FSG

       McbspbRegs.PCR.bit.CLKRP = 0;                   // MCLKR pin polarity: Falling edge on MCLKR pin genertes transitions on CLKG & FSG

       McbspbRegs.PCR.bit.CLKXM = 1;                   // Transmit clock mode: The MCLKX pin is an output pin driven by the sample rate generator of the McBSP.

       McbspbRegs.PCR.bit.SCLKME = 0;                  // Sample rate generator input clock mode bit

       McbspbRegs.SRGR2.bit.CLKSM = 1;                 // if SCLKME:0 and CLKSM:1 == i/p clk for sample rate generator = LSPCLK

      

       McbspbRegs.SRGR1.bit.CLKGDV = 0x24;            

       McbspbRegs.PCR.bit.FSXM = 1;                    // Transmit frame-synchronization mode

       McbspbRegs.SRGR2.bit.FSGM = 0;                  // Sample rate generator transmit frame-synchronization mode

       McbspbRegs.PCR.bit.FSXP = 1;                    // Transmit frame-synchronization polarity

       //

       McbspbRegs.RCR2.bit.RPHASE = 0;                 // For Dual-phase frame

       McbspbRegs.XCR2.bit.XPHASE = 0;                 // For Dual-phase frame

       McbspbRegs.RCR2.bit.RDATDLY=01;                 // Receive data delay bits.   1: 1-bit data delay

       McbspbRegs.XCR2.bit.XDATDLY=01;                 // Transmit data delay bits.  1: 1-bit data delay

 

       McbspbRegs.RCR1.bit.RWDLEN1=5;                  // 0=8, 5=32-bit word      2=16-bit word

       McbspbRegs.XCR1.bit.XWDLEN1=5;                  // 0=8, 5=32-bit word

       McbspbRegs.RCR2.bit.RWDLEN2=5;                  // 0=8, 5=32-bit word      2=16-bit word

       McbspbRegs.XCR2.bit.XWDLEN2=5;                  // 0=8, 5=32-bit word

 

       McbspbRegs.XCR1.bit.XFRLEN1=3;                  // four word in phase 1 transmit: one word = 32 bit

       McbspbRegs.RCR1.bit.RFRLEN1=3;                  // four word in phase 1 receive:  one word = 32 bit

      

       McbspbRegs.SPCR2.bit.GRST=1;                    // Enable the sample rate generator

       delay_loop();                                                 // Wait at least 2 SRG clock cycles

       McbspbRegs.SPCR2.bit.XRST=1;                    // Release TX from Reset

       McbspbRegs.SPCR1.bit.RRST=1;                    // Release RX from Reset

       McbspbRegs.SPCR2.bit.FRST=1;                    // Frame Sync Generator reset

}

 

unsigned long long MCP2317_Write_U33(Uint32 uvdata, Uint32 wdata)

{

       data1 = uvdata;

       uvdata >>= 16;

       data2 = uvdata;

 

       data3 = wdata;

       wdata >>=16;

       data4 = wdata;

 

 

       // Transmit 127 - 96 bit data

       while(McbspbRegs.SPCR2.bit.XRDY== 0) {}

              McbspbRegs.DXR2.all= sdata4;                          // 127-112

              McbspbRegs.DXR1.all= sdata3;                           // 111-96

      

       // Receive 127 -96 bit data

       while(McbspbRegs.SPCR1.bit.RRDY == 0) {}                            

              rdata22= McbspbRegs.DRR2.all & 0xffff;                 // 127-112:

              rdata11= McbspbRegs.DRR1.all & 0xffff;                 // 111-96 :

 

       // Transmit 95 - 64 bit data

       while(McbspbRegs.SPCR2.bit.XRDY== 0) {}

              McbspbRegs.DXR2.all= sdata2;                           // 95-80

              McbspbRegs.DXR1.all= sdata1;                           // 79-64

 

       // Receive 95 - 64 bit data

       while(McbspbRegs.SPCR1.bit.RRDY == 0) {}

              rdata44= McbspbRegs.DRR2.all & 0xffff;                 // 95-80  :

              rdata33= McbspbRegs.DRR1.all & 0xffff;                 // 79-64  :

      

       // Transmit 63 - 32 bit data

       while(McbspbRegs.SPCR2.bit.XRDY== 0) {}

              McbspbRegs.DXR2.all= data2;                             // 63-48

              McbspbRegs.DXR1.all= data1;                            // 47-32

 

       // Receive 63 - 32 bit data

       while(McbspbRegs.SPCR1.bit.RRDY == 0) {}

              rdata2= McbspbRegs.DRR2.all & 0xffff;                  // 63-48: v

              rdata1= McbspbRegs.DRR1.all & 0xffff;                  // 47-32: u

 

       // Transmit 31 - 0 bit data

       while(McbspbRegs.SPCR2.bit.XRDY== 0) {}

              McbspbRegs.DXR2.all= data4;                             // 31-16

              McbspbRegs.DXR1.all= data3;                            // 15-0

 

       // Receive 31 - 0 bit data

       while(McbspbRegs.SPCR1.bit.RRDY == 0) {}

              rdata4= McbspbRegs.DRR2.all & 0xffff;                  // 31-16: w

              rdata3= McbspbRegs.DRR1.all & 0xffff;                  // 15-0 : CRC + fault data

 

       // Received Data 127-64 bit

       r_data_new = rdata22;

       r_data_new <<= 16;

       r_data_new = r_data_new | rdata11;

       r_data_new <<= 16;

       r_data_new = r_data_new | rdata44;

       r_data_new <<= 16;

       r_data_new = r_data_new | rdata33;

 

       // Received Data 63-0 bit

       r_data = rdata2;

       r_data <<= 16;

       r_data = r_data | rdata1;

       r_data <<= 16;

       r_data = r_data | rdata4;

       r_data <<= 16;

       r_data = r_data | rdata3;

}