Tool/software: Code Composer Studio
Hi,
I am using the following CCS program for Help for sinusoidal PWM for three phase inverter.
I am getting the output but I have doubt on sampling time, particularly following two lines
sample_time = 20000.0/(200.0*a);
ConfigCpuTimer(&CpuTimer0,150,sample_time);
How much sampling time should be taken. For different samples iam getting variation in outputs.
please help. If you have other code for sinusoidal PWM for three phase inverter, please send.
The following is the program:
void main(void)
{
InitSysCtrl(); // Basic Core Init from DSP2833x_SysCtrl.c
EALLOW;
SysCtrlRegs.WDCR= 0x00AF; // Re-enable the watchdog
EDIS; // 0x00AF to NOT disable the Watchdog, Prescaler = 64
DINT; // Disable all interrupts
Gpio_select(); // To select required pins as output
InitPieCtrl(); // basic setup of PIE table;
InitPieVectTable(); // default ISR's in PIE
EALLOW;
PieVectTable.TINT0 = &cpu_timer0_isr;
EDIS;
InitCpuTimers(); // basic setup CPU Timer0, 1 and 2
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
IER |=1; // enable INT3 for ePWM1
EINT;
ERTM;
Setup_ePWM1(); // init of ePWM pins
sample_time = 20000.0/(200.0*a);
ConfigCpuTimer(&CpuTimer0,150,sample_time);
CpuTimer0Regs.TCR.bit.TSS = 0; // start timer0
while(1)
{
while(CpuTimer0.InterruptCount == 0);
CpuTimer0.InterruptCount = 0;
EALLOW;
SysCtrlRegs.WDKEY = 0x55; // service WD #1
EDIS;
sine_value1 = (a*sin(2*3.141593*index/200.0)+0.9999)/2.0;
EPwm1Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD - _IQsat(_IQ10mpy(_IQ10(sine_value1),EPwm1Regs.TBPRD),EPwm1Regs.TBPRD,0);
sine_value2 = (a*sin((2*3.141593*index/200.0)+(2*3.141593/3))+0.9999)/2.0;
EPwm2Regs.CMPA.half.CMPA = EPwm2Regs.TBPRD - _IQsat(_IQ10mpy(_IQ10(sine_value2),EPwm2Regs.TBPRD),EPwm2Regs.TBPRD,0);
sine_value3 = (a*sin((2*3.141593*index/200.0)+(4*3.141593/3))+0.9999)/2.0;
EPwm3Regs.CMPA.half.CMPA = EPwm3Regs.TBPRD - _IQsat(_IQ10mpy(_IQ10(sine_value3),EPwm3Regs.TBPRD),EPwm3Regs.TBPRD,0);
index +=1; // go to next sample
if (index >199) index = 0;
} // End of while loop
}// End of main()
void Gpio_select(void)
{
EALLOW;
GpioCtrlRegs.GPAMUX1.all = 0; // GPIO15 ... GPIO0 = General Puropse I/O
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // ePWM1A active
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // ePWM1B active
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // ePWM2A active
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // ePWM2B active
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // ePWM3A active
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // ePWM3B active
GpioCtrlRegs.GPAMUX2.all = 0; // GPIO31 ... GPIO16 = General Purpose I/O
GpioCtrlRegs.GPBMUX1.all = 0; // GPIO47 ... GPIO32 = General Purpose I/O
GpioCtrlRegs.GPBMUX2.all = 0; // GPIO63 ... GPIO48 = General Purpose I/O
GpioCtrlRegs.GPCMUX1.all = 0; // GPIO79 ... GPIO64 = General Purpose I/O
GpioCtrlRegs.GPCMUX2.all = 0; // GPIO87 ... GPIO80 = General Purpose I/O
GpioCtrlRegs.GPADIR.all = 0;
GpioCtrlRegs.GPBDIR.all = 0xFFFFFFFF; //
GpioCtrlRegs.GPCDIR.all = 0xFFFFDFFF; //
EDIS;
}
void Setup_ePWM1(void)
{
//EPwm1Regs.TBCTL.all = 0xC932;
EPwm1Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm1Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm1Regs.AQCTLA.all = 0x0060; // set ePWM1A on CMPA up
EPwm1Regs.TBPRD = (150000*1000/(2100*2.0)); // timer period for 2.100 KHz
EPwm1Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD / 2; // 50% duty cycle first
EPwm1Regs.CMPB = EPwm1Regs.TBPRD / 2;
EPwm1Regs.DBRED = 19; // 2 microseconds dead-band
EPwm1Regs.DBFED = 19;
EPwm1Regs.DBCTL.bit.OUT_MODE = 3;
EPwm1Regs.DBCTL.bit.POLSEL = 2;
EPwm1Regs.DBCTL.bit.IN_MODE = 0;
//---------------------------------------------------------------------------------------------
EPwm2Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm2Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm2Regs.AQCTLA.all = 0x0060; // set ePWM2A on CMPA up
EPwm2Regs.TBPRD = (150000*1000/(2100*2.0)); // timer period for 2.100 KHz
EPwm2Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD / 2; // 50% duty cycle first
EPwm2Regs.CMPB = EPwm1Regs.TBPRD / 2;
EPwm2Regs.DBRED = 19; // 2 microseconds dead-band
EPwm2Regs.DBFED = 19;
EPwm2Regs.DBCTL.bit.OUT_MODE = 3;
EPwm2Regs.DBCTL.bit.POLSEL = 2;
EPwm2Regs.DBCTL.bit.IN_MODE = 0;
//---------------------------------------------------------------------------------------------
EPwm3Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm3Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm3Regs.AQCTLA.all = 0x0060; // set ePWM2A on CMPA up
EPwm3Regs.TBPRD = (150000*1000/(2100*2.0)); // timer period for 2.100 KHz
EPwm3Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD / 2; // 50% duty cycle first
EPwm3Regs.CMPB = EPwm1Regs.TBPRD / 2;
EPwm3Regs.DBRED = 19; // 2 microseconds dead-band
EPwm3Regs.DBFED = 19;
EPwm3Regs.DBCTL.bit.OUT_MODE = 3;
EPwm3Regs.DBCTL.bit.POLSEL = 2;
EPwm3Regs.DBCTL.bit.IN_MODE = 0;
//---------------------------------------------------------------------------------------------
EPwm1Regs.ETSEL.all = 0;
EPwm1Regs.ETSEL.bit.INTEN = 1; // interrupt enable for ePWM1
EPwm1Regs.ETSEL.bit.INTSEL = 5; // interrupt on CMPA down match
EPwm1Regs.ETPS.bit.INTPRD = 1; // interrupt on first event
EPwm2Regs.ETSEL.all = 0;
EPwm2Regs.ETSEL.bit.INTEN = 1; // interrupt enable for ePWM2
EPwm2Regs.ETSEL.bit.INTSEL = 5; // interrupt on CMPA down match
EPwm2Regs.ETPS.bit.INTPRD = 1; // interrupt on first event
EPwm3Regs.ETSEL.all = 0;
EPwm3Regs.ETSEL.bit.INTEN = 1; // interrupt enable for ePWM2
EPwm3Regs.ETSEL.bit.INTSEL = 5; // interrupt on CMPA down match
EPwm3Regs.ETPS.bit.INTPRD = 1; // interrupt on first event
}
interrupt void cpu_timer0_isr(void)
// ISR runs every 2000 ns (PWM-frequency = 500 KHz)
// and is triggered by ePWM1 compare event
// run - time of ISR is 630 ns
{
CpuTimer0.InterruptCount++;
// Service watchdog every interrupt
EALLOW;
SysCtrlRegs.WDKEY = 0xAA; // Service watchdog #2
EDIS;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
