Part Number: TMS320F28377S
Other Parts Discussed in Thread: UNIFLASH, CONTROLSUITE
Tool/software: Code Composer Studio
Hi
I have some FW with DCSM Z1 settings provided in linker output file. This is fine for first time flashing. It is also fine for 2nd programming attempt without unsecuring, it just fails but unit keeps working with old FW. But I had to unsecure, debug and flash new version.
I've pulled one of boot pins to choose wait mode, I edited GEL file to make Z1 unsecured using known Z1 passwords when I click CPU reset button in IDE. I did some debugging in RAM (without changing any bit in OTP), then I flashed new code to my failure *with the same old OTP zone config in linker output file*, it failed. Then I flashed code without built in OUT file zone config settings. It succeded, but code doesn’t start (of course with both boot pins pulled high)! It starts if change zone link pointer to the next zone with blank password. Why? Did OTP ECC get damaged? How and where to see evidence of this in registers? I loaded symbols from ROM out file, every time I click CPU reset and Resume it stops in WaitBoot routine at ESTOP instruction. I tried debugging ROM for why it ends there, but it is too difficult to understand with tons of various OTP settings. If after clicking CPU Reset I edit PC pointer to entry point of my FW, it works as expected. What I'm sure about is that boot ROM doesn't do any attempt to call anything in flash.
Could anyone help with this? Why doesn’t it run anymore? If it’s due to OTP ECC, then how to verify this? I see no single change in Flash ECC regs between the moment after clicking CPU reset and when it stops on ESTOP in WaitBoot() in ROM.
Also I wonder why security is made OTP so that single failure may easily lead to broken device or even expensive produced unit? Why not flash, which could be erased even not having known unlock password? Perhaps it was not easy for TI, OK, but why EVERYTHING is reversed!?!? Uniflash lists passwords from 3rd down to 0th. CCS flash settings list them from 0th to 3rd. By address order of settings in zone config is EXEONLYRAM-EXEONLYSECT-GRABRAM-GRABSECT. Why then CCS shuffled them in flash settings? OK, it is as is, but how is it supposed to be handled easily? CCS – no. Uniflash – no. Providing DCSM settings in ELF file is easy for the first time. What if some servicing is required, unlock, then lock again? How to do it without the grief?
Update: I checked Boot ROM Status register at 0x2C. Comparing CPU Reset - Resume sequence, unsecured vs secured is 0x0000F000 vs 0x0000D000. In secured bit 9 Flash boot has started is not set. Error bits 17.. 30 are clear in both cases.
Update2: Tried engaging Z2. First of all CCS (v8) refused to program PSWDLOCK=0 for Z2. Seems like CCS bug.
With Z2 it is the same, enabled security - no operation, disabled security - operates OK.
Regarding Boot ROM Status. It turns that my understanding about EMUKEY etc was wrong. Since I was secured board up with boot pins set to Wait, no wonder that it landed in WaitBoot() function. But setting EMUKEY for example to 0x0B5A (boot from flash), clicking CPU Reset and Resume, connection with CPU always gets lost, connection not possible without board power cycle.
Thanks
Edward