TMS320F28335: Getting random bad data from A/D converter through DMA

//###########################################################################
//
// FILE:   Example_2833xAdcToDMA.c
//
// TITLE:  ADC to DMA Example
//
//! \addtogroup f2833x_example_list
//! <h1> ADC to DMA (adc_dma)</h1>
//!
//! This ADC example uses ADC to convert 4 channels for each SOC received,
//! with total of 10 SOCs.
//! Each SOC initiates 4 conversions.
//! DMA is used to capture the data on each SEQ1_INT. DMA will re-sort
//! the data by channel sequentially, i.e. all channel0 data will be
//! together and all channel1 data will be together.
//!
//! \b Watch \b Variables \n
//! - DMABuf1	- DMA Buffer
//
//###########################################################################
// $TI Release: F2833x Support Library v2.00.00.00 $
// $Release Date: Sun Mar 25 13:25:02 CDT 2018 $
// $Copyright:
// Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

//
// Defines for ADC start parameters
//
#if (CPU_FRQ_150MHZ)     // Default - 150 MHz SYSCLKOUT
    //
    // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)   = 25.0 MHz
    //
    #define ADC_MODCLK 0x3
#endif
#if (CPU_FRQ_100MHZ)
    //
    // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)   = 25.0 MHz
    //
    #define ADC_MODCLK 0x2
#endif

//
// ADC module clock = HSPCLK/2*ADC_CKPS   = 25.0MHz/(1*2) = 12.5MHz
//
#define BURST_SIZE 16

//
// Globals
//
Uint16 j=0;

#pragma DATA_SECTION(DMABuf1,"DMARAML4");
volatile Uint16 DMABuf1[32];

__interrupt void local_DINTCH1_ISR(void);
__interrupt void local_ADC_ISR(void);

/*
__interrupt void local_EPWM1_ISR(void);
__interrupt void local_EPWM2_ISR(void);
*/

void init_adc( void );
void init_dma( void );
void init_pwm( void );

Uint16 junk;

volatile Uint16 *pSrc;
volatile Uint16 *pDst;

#define ADCINTPWMSIZE 10

Uint32 AdcIntCnt = 0;
Uint16 AdcIntPWM[ADCINTPWMSIZE][3];
Uint32 DmaIntCnt = 0;
Uint16 DmaIntPWM[ADCINTPWMSIZE/2];

//
// Main
//
void main(void)
{
    //
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the DSP2833x_SysCtrl.c file.
    //
    InitSysCtrl();

    //
    // Specific clock setting for this example
    //
    EALLOW;
    SysCtrlRegs.HISPCP.all = ADC_MODCLK;	// HSPCLK = SYSCLKOUT/ADC_MODCLK
    EDIS;

    //
    // Step 2. Initialize GPIO:
    // This example function is found in the DSP2833x_Gpio.c file and
    // illustrates how to set the GPIO to it's default state.
    //
    // InitGpio();  // Skipped for this example

    //
    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts
    //
    DINT;

    //
    // Initialize the PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the DSP2833x_PieCtrl.c file.
    //
    InitPieCtrl();

    //
    // Disable CPU interrupts and clear all CPU interrupt flags:
    //
    IER = 0x0000;
    IFR = 0x0000;

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in DSP2833x_DefaultIsr.c.
    // This function is found in DSP2833x_PieVect.c.
    //
    InitPieVectTable();

    //
    // Interrupts that are used in this example are re-mapped to
    // ISR functions found within this file.
    //
    EALLOW;	// Allow access to EALLOW protected registers
    PieVectTable.DINTCH1   = &local_DINTCH1_ISR;
    PieVectTable.SEQ1INT   = &local_ADC_ISR;
/*
    PieVectTable.EPWM1_INT = &local_EPWM1_ISR;
    PieVectTable.EPWM2_INT = &local_EPWM2_ISR;
*/
    EDIS;   // Disable access to EALLOW protected registers

    IER = M_INT7 | M_INT1; // M_INT3 |
    EnableInterrupts();

    //
    // Step 4. Initialize all the Device Peripherals:
    // This function is found in DSP2833x_InitPeripherals.c
    //
    // InitPeripherals(); // Not required for this example
    EALLOW;
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0;
    GpioCtrlRegs.GPADIR.bit.GPIO31  = 1;
    EDIS;

    for(j=0;j<ADCINTPWMSIZE;j++) {
        AdcIntPWM[j][0] = 0;
        AdcIntPWM[j][1] = 0;
        AdcIntPWM[j][2] = 0;
    }

    for(j=0;j<(ADCINTPWMSIZE/2);j++) {
        DmaIntPWM[j] = 0;
    }

    init_adc();
    init_dma();
    init_pwm();

    //
    // For this example will re-start manually
    //
    while(1);
}

//
// local_DINTCH1_ISR - INT7.1(DMA Channel 1)
//
__interrupt void 
local_DINTCH1_ISR(void)
{
    Uint16 j;
    //
    // To receive more interrupts from this PIE group, acknowledge this 
    // interrupt
    //
    StartDMACH1();
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
    EALLOW;
    DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;
    EDIS;

    DmaIntPWM[DmaIntCnt%(ADCINTPWMSIZE/2)] = EPwm4Regs.TBCTR;

/*
    if((DmaIntCnt%(ADCINTPWMSIZE/2)) == ((ADCINTPWMSIZE/2)-1)) {
        asm(" ESTOP0");
    }
*/

    DmaIntCnt++;

    if( (DmaIntCnt % 0x2000) == 0 ) {
        GpioDataRegs.GPATOGGLE.bit.GPIO31 = 1; // Toggle LED
    }

    //
    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    //
    for(j=0;j<sizeof(DMABuf1);j++) {
        if( DMABuf1[j] == 0 ) {
            asm(" ESTOP0");
        }
    }
}


__interrupt void
local_ADC_ISR(void)
{
    //
    // To receive more interrupts from this PIE group, acknowledge this
    // interrupt
    //
    AdcIntPWM[AdcIntCnt%ADCINTPWMSIZE][0] = EPwm4Regs.TBCTR;
    AdcIntPWM[AdcIntCnt%ADCINTPWMSIZE][1] = EPwm2Regs.TBCTR;
    AdcIntPWM[AdcIntCnt%ADCINTPWMSIZE][2] = EPwm2Regs.TBSTS.bit.CTRDIR;

    if( (EPwm2Regs.TBCTR > (AdcIntPWM[AdcIntCnt%ADCINTPWMSIZE][1] - 650)) && (EPwm2Regs.TBSTS.bit.CTRDIR == 0) ) {
        pSrc = (volatile Uint16*)&AdcMirror.ADCRESULT0;
        pDst = (volatile Uint16*)&DMABuf1[16];
    } else {
        pSrc = (volatile Uint16*)&AdcMirror.ADCRESULT0;
        pDst = (volatile Uint16*)&DMABuf1[0];
    }

    AdcIntCnt++;

    for(j=0;j<16;j++) {
        if( *pSrc != *pDst ) {
            asm(" ESTOP0");
        }
        pSrc++;
        pDst++;
    }

    AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
    AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}


void init_adc( void )
{
    InitAdc();  // For this example, init the ADC

    // ADCTRL1 setup
    // AdcRegs.ADCTRL1.bit.SUSMOD = 01; // stop after current sequence
    // AdcRegs.ADCTRL1.bit.ACQ_PS = 0010; // acquisition size = 3
    // AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // cascaded sequencer mode
    // Everything else 0
//    AdcRegs.ADCTRL1.all = 0x10210;
    AdcRegs.ADCTRL1.bit.SUSMOD = 0;
    AdcRegs.ADCTRL1.bit.ACQ_PS = 2;
    AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;

    // ADCTRL2 setup
    // AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 1; // SOCB
    // AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // reset to CONV0
    // AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // enable SEQ1 interrupt
    // Everything else 0
//    AdcRegs.ADCTRL2.all = 0xC800;
    AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 1;
//    AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;
    AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
    AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;
    AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0;
    PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
    //PieCtrlRegs.PIEIER1.bit.INTx6 = 1;

    // Need a 25Mhz clock for ADC. ADC Clock is HSPCLK/2*ADCCLKPS
//    AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_MODCLK;

    //
    // * set sequence channels
    // * They need to be in the same order as the RawAdc struct!!
    //
    AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 8; // input current phA - B0
    AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 9; // input current phB - B1
    AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 10; // input current phC - B2
    AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0; // input voltage phA - A0
    AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 1; // input voltage phB - A1
    AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 2; // input voltage phC - A2
    AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 3; // dc link pos - A3
    AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 11; // dc link neg - B3

    AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 4; // output voltage - A4
    AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 12; // output current - B4
    AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 7; // output bus A - A7
    AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 14; // output bus B - B6

    AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 13; // internal temp
    AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 15; // unused
    AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 5; // IGBT temp
    AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 6; // low V sense
    AdcRegs.ADCMAXCONV.all = 15;
}


void init_dma( void )
{
    volatile Uint16* dmaDst = &DMABuf1[0];
    volatile Uint16* dmaSrc = &AdcMirror.ADCRESULT0;
    Uint16 j;

    for(j=0;j<sizeof(DMABuf1);j++) {
        DMABuf1[j] = 0xFFFF;
    }

    // initialize DMA hardware
    DMAInitialize();

    // configure dma source and destination addresses
    DMACH1AddrConfig( (Uint16*)dmaDst, dmaSrc );

    // 16 words/burst(X-1), increment source 1 word, increment dest 1 word
    DMACH1BurstConfig( (BURST_SIZE-1), 1, 1 );

    // 2 bursts/transfer(X-1), src transfer step, dest transfer step
    DMACH1TransferConfig( 1, 1, 1 );

    // wrap source after 1 burst, no offset, wrap dest after 2 bursts, no offset
    DMACH1WrapConfig( 0, 0, 1, 0 );

    // trigger source = ADC sequence1 interrupt, enable interrupt(from adc), disable one-shot and continuous,
    // no sync, 16-bit, interupt enabled(to cpu) at end of sequence
    DMACH1ModeConfig( DMA_SEQ1INT, PERINT_ENABLE, ONESHOT_DISABLE, CONT_DISABLE, SYNC_DISABLE, SYNC_SRC,
    OVRFLOW_DISABLE, SIXTEEN_BIT, CHINT_END, CHINT_ENABLE );

    StartDMACH1();
}


void init_pwm( void )
{
    #define PERIPHERAL_CLOCK        150000000
    #define LLC_INITIAL_FREQ        250000
    #define LLC_INIT_PWM_PERIOD        PERIPHERAL_CLOCK / LLC_INITIAL_FREQ / 2

    #define APWM_FREQ               20000
    #define APWM_PERIOD             PERIPHERAL_CLOCK / APWM_FREQ

    #define DEBUG_PWM_FREQ          200000
    #define DEBUG_PWM_PERIOD        PERIPHERAL_CLOCK / DEBUG_PWM_FREQ

    #define APWM_CMPR_OUTPUT        2750
    #define APWM_CMPR_INPUT         2000

    #define BURST_PERIOD            PERIPHERAL_CLOCK / 10000                            // Start with 10kHz

    // rectifier constants
    #define RECTIFIER_PWM_FREQ        30000                                                // pwm frequency in hertz
    #define RECTIFIER_PWM_PERIOD    PERIPHERAL_CLOCK / RECTIFIER_PWM_FREQ / 2            // timer period value (up/down counter)

    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;      // Stop all the TB clocks
    EDIS;

    EPwm1Regs.TBCTR = 1;
    EPwm2Regs.TBCTR = 1;
    EPwm3Regs.TBCTR = 1;
    EPwm4Regs.TBCTR = 1;
    EPwm5Regs.TBCTR = 1;
    EPwm6Regs.TBCTR = 1;

    EPwm1Regs.TBCTL.all = 0;
    EPwm2Regs.TBCTL.all = 0;
    EPwm3Regs.TBCTL.all = 0;
    EPwm4Regs.TBCTL.all = 0;
    EPwm5Regs.TBCTL.all = 0;
    EPwm6Regs.TBCTL.all = 0;
/*
    // Setup Sync
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;  // Sync source for rectifier
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;   // Pass through
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;   // Pass through
    EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;  // Sync source for dc/dc
    EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;   // Pass through
    EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;   // Pass through

    // Rectifier sync, dc/dc no sync
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;         // EPwm1 is sync source for rectifier
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;         // Sync EPwm2 to EPwm1
    EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;         // Sync EPwm3 to EPwm2
    EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;         //
    EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE;         // Start out disabled, sync is only for burst mode
    EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE;      // EPwm6 not currently used.

    EPwm1Regs.TBPHS.half.TBPHS = 0;                 // no phase shift between pwms
    EPwm2Regs.TBPHS.half.TBPHS = 0;
    EPwm3Regs.TBPHS.half.TBPHS = 0;
    EPwm4Regs.TBPHS.half.TBPHS = 0;
    EPwm5Regs.TBPHS.half.TBPHS = 0;
    EPwm6Regs.TBPHS.half.TBPHS = 0;
*/
    // STOP timers on emulator suspend
    EPwm1Regs.TBCTL.bit.FREE_SOFT = 0;
    EPwm2Regs.TBCTL.bit.FREE_SOFT = 0;
    EPwm3Regs.TBCTL.bit.FREE_SOFT = 0;
    EPwm4Regs.TBCTL.bit.FREE_SOFT = 0;
    EPwm5Regs.TBCTL.bit.FREE_SOFT = 0;
    EPwm6Regs.TBCTL.bit.FREE_SOFT = 0;

    // ePwmRegs.ETPS setup
    // 15:14 SOCBCNT            = 00
    // 13:12 SOCBPRD            = 01    generate on 1st event
    // 11:10 SOCACNT            = 00
    // 9:8 SOCAPRD              = 00
    // 7:4 reserved             = 0000
    // 3:2 INTCNT               = 00
    // 1:0 INTPRD               = 00
//    EPwm1Regs.ETPS.all = 0x1000;
    EPwm1Regs.ETPS.bit.SOCBPRD = ET_1ST;

    // setup a/d trigger from epwm1 and epwm2. Use zero on epwm1 and prd on epwm2
    // as SOC triggers to get a 50kHz sampling rate

    // 15 socBen                = 1     ePWM triggers SOCB
    // 14:12 socBsel            = 001   on timer 0
    // 11 socAen                = 0     no SOCA
    // 10:8 socAsel             = 000   na
    // 7:4 resvd                = 0000
    // 3 inten                  = 0     no ISR
    // 2:0 insel                = 000   NA
//    EPwm1Regs.ETSEL.all = 0x9000;
    EPwm1Regs.ETSEL.bit.SOCBEN = 1;
    EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTR_ZERO;
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPB;
/*
    EPwm1Regs.ETCLR.bit.INT   = 1;
    EPwm1Regs.ETSEL.bit.INTEN = 0;
    EPwm1Regs.ETPS.bit.INTPRD = 0;
    PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
*/

    // ePwmRegs.ETPS setup
    // 15:14 SOCBCNT            = 00
    // 13:12 SOCBPRD            = 01    generate on 1st event
    // 11:10 SOCACNT            = 00
    // 9:8 SOCAPRD              = 00
    // 7:4 reserved             = 0000
    // 3:2 INTCNT               = 00
    // 1:0 INTPRD               = 00
//    EPwm2Regs.ETPS.all = 0x1000;
    EPwm2Regs.ETPS.bit.SOCBPRD = ET_1ST;

    // 15 socBen                = 1     ePWM triggers SOCB
    // 14:12 socBsel            = 010   on timer prd
    // 11 socAen                = 0     no SOCA
    // 10:8 socAsel             = 000   na
    // 7:4 resvd                = 0000
    // 3 inten                  = 0     no ISR
    // 2:0 insel                = 000   NA
//    EPwm2Regs.ETSEL.all = 0xa000;
    EPwm2Regs.ETSEL.bit.SOCBEN = 1;
    EPwm2Regs.ETSEL.bit.SOCBSEL = ET_CTR_PRD;
    EPwm2Regs.ETSEL.bit.INTSEL = ET_CTRD_CMPB;
/*
    EPwm2Regs.ETCLR.bit.INT   = 1;
    EPwm2Regs.ETSEL.bit.INTEN = 0;
    EPwm2Regs.ETPS.bit.INTPRD = 0;
    PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
*/

    // EPwm1: Rectifier PHA
    EPwm1Regs.TBPRD = RECTIFIER_PWM_PERIOD;
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;       // Count up/down
//    EPwm1Regs.ETSEL.bit.INTEN = 0;                      // no interrupt
    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
//    EPwm1Regs.CMPB           = PWM_INT_OFFSET;

    // EPwm2: Rectifier PHB
    EPwm2Regs.TBPRD = RECTIFIER_PWM_PERIOD;
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;       // Count up/down
//    EPwm2Regs.ETSEL.bit.INTEN = 0;                       // no interrupt
    EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
    EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
//    EPwm2Regs.CMPB           = RECTIFIER_PWM_PERIOD - PWM_INT_OFFSET;

    // EPwm3: Rectifier PHC
    EPwm3Regs.TBPRD = RECTIFIER_PWM_PERIOD;
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;       // Count up/down
    EPwm3Regs.ETSEL.bit.INTEN = 0;                       // no interrupt
    EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;
    EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;

    // EPwm4, used for burst control
    // EPwm4 must be used so it can set the synchronisation point for EPwm5 not the other way around
    // (Burst control sets the syncronisation for general LLC operation, not the other way around)
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;          // Count up/down
    EPwm4Regs.ETSEL.bit.INTEN = 0;                      // no interrupt

    //EPwm4Regs.TBPRD = BURST_PERIOD;
    EPwm4Regs.TBPRD = 0xFFFF;

    // Assume no burst control at startup for the moment
    // Both held high to allow all pulses through
    EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;

    // 50% Duty
    EPwm4Regs.CMPA.half.CMPA = EPwm4Regs.TBPRD >> 1;
    EPwm4Regs.CMPB = EPwm4Regs.TBPRD >> 1;

    // Apply clock divider to allow for lower frequency range
//    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    // Allow software force of A and B outputs
    // Software force will set both outputs low
    EPwm4Regs.AQSFRC.bit.ACTSFA = 1;
    EPwm4Regs.AQSFRC.bit.ACTSFB = 1;

    // EPwm5: LLC primary gates
    EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;       // Count up/down
    EPwm5Regs.ETSEL.bit.INTEN = 0;                       // no interrupt
    // Set actions, single pwm output using the deadband module to create a complementary pair
    EPwm5Regs.TBPRD = LLC_INIT_PWM_PERIOD;
    EPwm5Regs.AQCTLA.bit.CAU = AQ_SET;
    EPwm5Regs.AQCTLA.bit.CAD = AQ_CLEAR;

    EPwm5Regs.DBCTL.bit.POLSEL = 2;                        // complementary active low
    EPwm5Regs.DBCTL.bit.OUT_MODE = 3;
    // 6.67ns per tick, 500ns desired deadtime.
    // DB reg = 500/6.67 ~= 33
    EPwm5Regs.DBFED = 33;
    EPwm5Regs.DBRED = 33;
    EPwm5Regs.CMPA.half.CMPA = EPwm4Regs.TBPRD >> 1;

    // EPwm6: routed to CPLD for debug purposes, otherwise not used.
    EPwm6Regs.TBPRD = DEBUG_PWM_PERIOD;
    EPwm6Regs.TBCTL.bit.CTRMODE= TB_COUNT_UP;              // Count up
    EPwm6Regs.ETSEL.bit.INTEN = 0;                       // no interrupt
    EPwm6Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm6Regs.AQCTLB.bit.ZRO = AQ_SET;
    EPwm6Regs.AQCTLB.bit.CBU = AQ_CLEAR;

    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;         // Start all the timers synced
    EDIS;
}


/*
__interrupt void
local_EPWM1_ISR(void)
{
    //
    // To receive more interrupts from this PIE group, acknowledge this
    // interrupt
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
    EPwm1Regs.ETCLR.bit.INT = 1;

    //
    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    //

    pSrc = (volatile Uint16*)&AdcMirror.ADCRESULT0;
    pDst = (volatile Uint16*)&DMABuf1[16];

    while(*pSrc != *pDst);
    asm(" ESTOP0");

    if(0 && (DmaIntCnt < 1) ) {
        // Skip first round before ADC has results
    } else {
        for(j=0;j<16;j++) {
            if( *pSrc != *pDst ) {
                asm(" ESTOP0");
            }
            pSrc++;
            pDst++;
        }
    }
}

__interrupt void
local_EPWM2_ISR(void)
{
    //
    // To receive more interrupts from this PIE group, acknowledge this
    // interrupt
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
    EPwm2Regs.ETCLR.bit.INT = 1;

    //
    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    //
    pSrc = (volatile Uint16*)&AdcMirror.ADCRESULT0;
    pDst = (volatile Uint16*)&DMABuf1[0];

    while(*pSrc != *pDst);
    asm(" ESTOP0");

    if(0 && (DmaIntCnt < 1) ) {
        // Skip first round before ADC has results
    } else {
        for(j=0;j<16;j++) {
            if( *pSrc != *pDst ) {
                asm(" ESTOP0");
            }
            pSrc++;
            pDst++;
        }
    }
}
*/

//
// End of File
//