CCS/TMS320F28035: Issue with epwm interrupt

S.Ibarra

Part Number: TMS320F28035
Other Parts Discussed in Thread: CONTROLSUITE

Tool/software: Code Composer Studio

Hi, All

Since a three weeks I am working to solve a issue with the epwm module interruption. I did review PIE, IER, PIEACK, PIEIER, PCLKR0 registers like also as configuration registers for epwm3, epwm4 and epwm5. However my code doesn´t
work, because the epwm5 don´t interrupt.

My application needs three epwm modules that working with a master an two slaves to generate a three phase SPWM signal. I´m using an experimenter kit with TMS320F28035 piccolo microcontroller and CCS V.7.

I need technical assitance, mainly of the TI staff. Someone knows how I can contact with them?

over 7 years ago

0 Subrahmanya over 7 years ago

TI__Mastermind 24095 points

Hi Ibarra,

Forum is the right place to contact and seek technical assistance.
Regarding the specifics of the issue, you can check the interrupt generation and processing in 3 stages.

1. Is the module generating interrupt?
Please check the ETFLG register of the corresponding EPWM is set. If it's already set, clear it and make sure that it's set at the intended time.
If this step is not working, that means some wrong configuration of module or interrupt.
2. Once the Interrupt is generated from the module, it is transferred to pie. Check IER/ACK etc - i'm assuming these are fine as you've mentioned that you've already reviewed these regs.
3. CPU executing ISR - Is it executing some random/uninitialized code? If so, it would be appropriate to check the PieVector table ISR address.

Please provide more details of the exact issue you.

-Bharathi.

0 S.Ibarra over 7 years ago in reply to Subrahmanya

Intellectual 655 points

Hi Bharathi

I did a debug exercise with CCS v.7. I'am trying use epwm3 (master), epwm4 (first slave) and epwm5 (second slave), to generate a three phase SPWM signal. At follow I show the content of the registers of microcontroller.

PIECTRL = 0x0D65. This implies that epwm3 interrupt arrived. CORRECT
PIECTRL = 0x0D67. This implies that epwm4 interrupt arrived. CORRECT
PIECTRL = 0x0D41. This implies that ADC_INT1interrupt arrived. CORRECT.
But doesn´t arrives the interrupt of epwm5.

PIEACK Shows two states
PIEACK = 0x0004 and PIEACK = 0x0005. This implies that an interrupt of group3 has been sent to the cpu.

PIEIER = 0x001C. Without change. This register shows that the epwm3, 4, and 5 are enabled.

epwm3 and epwm4 generate their respective interrupts.

In the case of epwm5 registers:
ETSEL = 0x0009. INTSEL = 001 Enable event time-base counter equal to zero
INTEN = 1. Enable EPWMx_INT generation.

ETPS = 0x0005. INTPRD = 01. Generate an interrupt on the first event
INTCNT = 1. 1 event has ocurred.
ETFLG = 0x0001. Indicates that an epwm5 interrupt was generate.

In the case of CPU registers:

IER changes betwen two values
IER = 0x00FF. Enable interrupts 1-7.
IER = 0x00FB. Disable interrupt 3

Furthermore I send the screenviews of configuration of epwm.

Thanks a lot.

Sebastián

Fullscreen EPwm_7_8_9_10_12.c Download

/**********************************************************************
* File: EPwm_7_8_9_10_12.c -- File for Lab 7, 8, 9, 10 and 12
* Devices: TMS320F2803x
* Author: Technical Training Organization (TTO), Texas Instruments
* History:
*   09/15/09 - original
**********************************************************************/

#include "Lab.h"				// Main include file

//DINT;                           // Inhhibe las interrupciones del CPU

// IER = 0x0000;
// IFR = 0x0000;

/**********************************************************************
* Function: InitEPwm()
*
* Description: Initializes the Enhanced PWM modules on the F2803x
**********************************************************************/
void InitEPwm(void)
{
//---------------------------------------------------------------------
//--- Must disable the clock to the ePWM modules if you       
//--- want all ePMW modules synchronized.
//---------------------------------------------------------------------
	asm(" EALLOW");						// Enable EALLOW protected register access
	SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
	asm(" EDIS");						// Disable EALLOW protected register access


//---------------------------------------------------------------------
//--- Configure ePWM2 to trigger the ADC at a 50 kHz rate   
//---------------------------------------------------------------------
	EPwm2Regs.TBCTL.bit.CTRMODE = 0x3;		// Disable the timer

	EPwm2Regs.TBCTL.all = 0xC033;			// Configure timer control register
// bit 15-14     11:     FREE/SOFT, 11 = ignore emulation suspend
// bit 13        0:      PHSDIR, 0 = count down after sync event
// bit 12-10     000:    CLKDIV, 000 => TBCLK = HSPCLK/1
// bit 9-7       000:    HSPCLKDIV, 000 => HSPCLK = SYSCLKOUT/1
// bit 6         0:      SWFSYNC, 0 = no software sync produced
// bit 5-4       11:     SYNCOSEL, 11 = sync-out disabled
// bit 3         0:      PRDLD, 0 = reload PRD on counter=0
// bit 2         0:      PHSEN, 0 = phase control disabled
// bit 1-0       11:     CTRMODE, 11 = timer stopped (disabled)

	EPwm2Regs.TBCTR = 0x0000;				// Clear timer counter
	EPwm2Regs.TBPRD = ADC_SAMPLE_PERIOD;	// Set timer period
	EPwm2Regs.TBPHS.half.TBPHS = 0x0000;	// Set timer phase

	EPwm2Regs.ETPS.all = 0x0100;			// Configure SOCA
// bit 15-14     00:     EPWMxSOCB, read-only
// bit 13-12     00:     SOCBPRD, don't care
// bit 11-10     00:     EPWMxSOCA, read-only
// bit 9-8       01:     SOCAPRD, 01 = generate SOCA on first event
// bit 7-4       0000:   reserved
// bit 3-2       00:     INTCNT, don't care
// bit 1-0       00:     INTPRD, don't care

	EPwm2Regs.ETSEL.all = 0x0A00;			// Enable SOCA to ADC
// bit 15        0:      SOCBEN, 0 = disable SOCB
// bit 14-12     000:    SOCBSEL, don't care
// bit 11        1:      SOCAEN, 1 = enable SOCA
// bit 10-8      010:    SOCASEL, 010 = SOCA on PRD event
// bit 7-4       0000:   reserved
// bit 3         0:      INTEN, 0 = disable interrupt
// bit 2-0       000:    INTSEL, don't care

	EPwm2Regs.TBCTL.bit.CTRMODE = 0x0;		// Enable the timer in count up mode


//---------------------------------------------------------------------
//--- Configure ePWM1 for 2 kHz symmetric PWM on EPWM1A pin    
//---------------------------------------------------------------------
	EPwm1Regs.TBCTL.bit.CTRMODE = 0x3;		// Disable the timer

	EPwm1Regs.TBCTL.all = 0xC033;			// Configure timer control register
// bit 15-14     11:     FREE/SOFT, 11 = ignore emulation suspend
// bit 13        0:      PHSDIR
// bit 12-10     000:    CLKDIV
// bit 9-7       000:    HSPCLKDIV
// bit 6         0:      SWFSYNC
// bit 5-4       11:     SYNCOSEL
// bit 3         0:      PRDLD
// bit 2         0:      PHSEN
// bit 1-0       11:     CTRMODE, 11 = timer stopped (disabled)

	EPwm1Regs.TBCTR = 0x0000;				// Clear timer counter
	EPwm1Regs.TBPRD = PWM_HALF_PERIOD;  	// Set timer period
	EPwm1Regs.TBPHS.half.TBPHS = 0x0000;	// Set timer phase

	EPwm1Regs.CMPA.half.CMPA =PWM_DUTY_CYCLE;	// Set PWM duty cycle

	EPwm1Regs.CMPCTL.all = 0x0002;          // Compare control register
// bit 15-10     0's:    reserved
// bit 9         0:      SHDWBFULL
// bit 8         0:      SHDWAFULL
// bit 7         0:      reserved
// bit 6         0:      SHDWBMODE
// bit 5         0:      reserved
// bit 4         0:      SHDWAMODE
// bit 3-2       00:     LOADBMODE
// bit 1-0       10:     LOADAMODE

	EPwm1Regs.AQCTLA.all = 0x0060;  		// Action-qualifier control register A
// bit 15-12     0000:   reserved
// bit 11-10     00:     CBD do nothing
// bit 9-8       00:     CBU do nothing
// bit 7-6       11:     CAD toggle
// bit 5-4       00:     CAU do nothing
// bit 3-2       00:     PRD do nothing
// bit 1-0       00:     ZRO do nothing

	EPwm1Regs.AQSFRC.all = 0x0000;		// Action-qualifier s/w force register
// bit 15-8      0's:    reserved
// bit 7-6       00:     RLDCSF, 00 = reload AQCSFRC on zero
// bit 5         0:      OTSFB, 0 = do not initiate a s/w forced event on output B
// bit 4-3       00:     ACTSFB, don't care
// bit 2         0:      OTSFA, 0 = do not initiate a s/w forced event on output A
// bit 1-0       00:     ACTSFA, don't care

	EPwm1Regs.AQCSFRC.all = 0x0000;		// Action-qualifier continuous s/w force register
// bit 15-4      0's:    reserved
// bit 3-2       00:     CSFB, 00 = forcing disabled
// bit 1-0       00:     CSFA, 00 = forcing disabled

	EPwm1Regs.DBCTL.bit.OUT_MODE = 0;	// Deadband disabled
	EPwm1Regs.PCCTL.bit.CHPEN = 0;		// PWM chopper unit disabled
	EPwm1Regs.TZDCSEL.all = 0x0000;		// All trip zone and DC compare actions disabled

	EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;	// Enable the timer in count up/down mode


	//=====================================================================
	// Config.
	// Initialization Time. Spruge9e.ePWM.pdf example, page 96 SIR
	//========================
	// EPWM Module 4 config
	EPwm3Regs.TBPRD = 500; // Period = 900 TBCLK counts
	EPwm3Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
	EPwm3Regs.TBCTL.bit.CTRMODE = 0x2;   // TB_COUNT_UPDOWN; // Symmetrical mode
	EPwm3Regs.TBCTL.bit.PHSEN = 0;       // TB_DISABLE; // Master module
	EPwm3Regs.TBCTL.bit.PRDLD = 0;       // TB_SHADOW;
	EPwm3Regs.TBCTL.bit.SYNCOSEL = 0x1;  // TB_CTR_ZERO; // Sync down-stream module

    EPwm3Regs.TBCTL.bit.FREE_SOFT=0x03;           // Configure timer control register	included by SIR

	EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;  // CC_SHADOW;
	EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;  // CC_SHADOW;
	EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;  // CC_CTR_ZERO; // load on CTR=Zero
	EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;  // CC_CTR_ZERO; // load on CTR=Zero
	EPwm3Regs.AQCTLA.bit.CAU = 0x2;      // AQ_SET; // set actions for EPWM1A
	EPwm3Regs.AQCTLA.bit.CAD = 0x1;      // AQ_CLEAR;
	EPwm3Regs.DBCTL.bit.OUT_MODE = 0x3;  // DB_FULL_ENABLE; // enable Dead-band module
	EPwm3Regs.DBCTL.bit.POLSEL = 0x2;    // DB_ACTV_HIC; // Active Hi complementary
	EPwm3Regs.DBFED = 20; // FED = 20 TBCLKs
	EPwm3Regs.DBRED = 20; // RED = 20 TBCLKs
	EPwm3Regs.ETPS.bit.INTPRD = 0x01;     // Genera int despues del primer evento

    asm(" EALLOW");                       // Enable EALLOW protected register access

    PieCtrlRegs.PIEIER3.bit.INTx3 = 1;    // Habilita INT del PWM4 del grupo 3

	EPwm3Regs.ETSEL.bit.INTSEL =0x1;       // Interrupcion cuando el contador es cero
	EPwm3Regs.ETSEL.bit.INTEN = 1;        // Habilita interrucion
    EPwm3Regs.TBCTR = 0x0000;             // Clear timer counter Included by SIR


//    PieCtrlRegs.PIEIER3.all =  0xFFFF;
//    PieCtrlRegs.PIEIER4.all =  0xFFFF;
    PieCtrlRegs.PIEACK.all = 0x0000;      // Enable PIE interrupts
    IER |= 0x00FF;                              // Enable INT1 in IER to enable PIE group

    asm(" EDIS");                       // Disable EALLOW protected register access
 //********************************



//************************************

	// EPWM Module 5 config.
	EPwm4Regs.TBPRD = 500; // Period = 900 TBCLK counts
	EPwm4Regs.TBPHS.half.TBPHS = 333;   // Phase = 300/900 * 360 = 120 deg ************************************
	EPwm4Regs.TBCTL.bit.CTRMODE = 0x2;   // TB_COUNT_UPDOWN; // Symmetrical mode
	EPwm4Regs.TBCTL.bit.PHSEN = 0x1;     // TB_ENABLE; // Slave module
	EPwm4Regs.TBCTL.bit.PHSDIR = 0;      // TB_DOWN; // Count DOWN on sync (=120 deg)
	EPwm4Regs.TBCTL.bit.PRDLD = 0;       // TB_SHADOW;
	EPwm4Regs.TBCTL.bit.SYNCOSEL = 0;    // TB_SYNC_IN; // sync flow-through OBSERVAR CONFIGURACI�N PROPUESTA

    EPwm4Regs.TBCTL.bit.FREE_SOFT = 0x03;           // Configure timer control register included by SIR

	EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;  // CC_SHADOW;
	EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;  // CC_SHADOW;
	EPwm4Regs.CMPCTL.bit.LOADAMODE = 0;  //CC_CTR_ZERO; // load on CTR=Zero
	EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;  // CC_CTR_ZERO; // load on CTR=Zero
	EPwm4Regs.AQCTLA.bit.CAU = 0x2;      // AQ_SET; // set actions for EPWM2A
	EPwm4Regs.AQCTLA.bit.CAD = 0x1;      // AQ_CLEAR;
	EPwm4Regs.DBCTL.bit.OUT_MODE = 0x3;  // DB_FULL_ENABLE; // enable Dead-band module
	EPwm4Regs.DBCTL.bit.POLSEL = 0x2;    // DB_ACTV_HIC; // Active Hi Complementary
	EPwm4Regs.DBFED = 20; // FED = 20 TBCLKs
	EPwm4Regs.DBRED = 20; // RED = 20 TBCLKs
//    EPwm5Regs.ETSEL.bit.INTSEL = 1;      // Interrupcion cuando el contador es cero
//    EPwm5Regs.ETSEL.bit.INTEN = 1;       // Habilita interrucion
//********************************************************************************************
    EPwm4Regs.ETPS.bit.INTPRD = 0x01;     // Genera int despues del primer evento

    asm(" EALLOW");                       // Enable EALLOW protected register access

    PieCtrlRegs.PIEIER3.bit.INTx4 = 1;    // Habilita INT del PWM5 del grupo 3

    EPwm4Regs.ETSEL.bit.INTSEL =0x1;       // Interrupcion cuando el contador es cero
    EPwm4Regs.ETSEL.bit.INTEN = 1;        // Habilita interrucion
    EPwm4Regs.TBCTR = 0x0000;             // Clear timer counter Included by SIR

//    PieCtrlRegs.PIEIER3.all =  0xFFFF;
//    PieCtrlRegs.PIEIER4.all =  0xFFFF;
    PieCtrlRegs.PIEACK.all = 0x0000;      // Enable PIE interrupts
    IER |= 0x00FF;                              // Enable INT1 in IER to enable PIE group

    asm(" EDIS");                       // Disable EALLOW protected register access
 //********************************

	EPwm4Regs.TBCTR = 0x0000;               // Clear timer counter Included by SIR
//    EPwm6Regs.ETCLR.bit.INT = 1;                // Limpia bandera de interrupcion ******************************

	// EPWM Module 6 config
	EPwm5Regs.TBPRD = 500; // Period = 900 TBCLK counts
	EPwm5Regs.TBPHS.half.TBPHS = 333; // Phase = 300/900 * 360 = 120 deg*************************************************
	EPwm5Regs.TBCTL.bit.CTRMODE = 0x2;   // TB_COUNT_UPDOWN; // Symmetrical mode
	EPwm5Regs.TBCTL.bit.PHSEN = 0x1;     // TB_ENABLE; // Slave module
	EPwm5Regs.TBCTL.bit.PHSDIR = 0x1;    // TB_UP; // Count UP on sync (=240 deg)
	EPwm5Regs.TBCTL.bit.PRDLD = 0;       // TB_SHADOW;
	EPwm5Regs.TBCTL.bit.SYNCOSEL = 0;    // TB_SYNC_IN; // sync flow-through

    EPwm5Regs.TBCTL.bit.FREE_SOFT = 0x03;           // Configure timer control register included by SIR

	EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;  // CC_SHADOW;
	EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;  // CC_SHADOW;
	EPwm5Regs.CMPCTL.bit.LOADAMODE = 0;  // CC_CTR_ZERO; // load on CTR=Zero
	EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;  // CC_CTR_ZERO; // load on CTR=Zero
	EPwm5Regs.AQCTLA.bit.CAU = 0x2;      // AQ_SET; // set actions for EPWM3Ai
	EPwm5Regs.AQCTLA.bit.CAD = 0x1;      // AQ_CLEAR;
	EPwm5Regs.DBCTL.bit.OUT_MODE = 0x3;  // DB_FULL_ENABLE; // enable Dead-band module
	EPwm5Regs.DBCTL.bit.POLSEL = 0x2;    // DB_ACTV_HIC; // Active Hi complementary
	EPwm5Regs.DBFED = 20; // FED = 20 TBCLKs
	EPwm5Regs.DBRED = 20; // RED = 20 TBCLKs
//    EPwm6Regs.ETSEL.bit.INTSEL = 1;      // Interrupcion cuando el contador es cero
//    EPwm6Regs.ETSEL.bit.INTEN = 1;       // Habilita interrucion
	//********************************************************************************************
	    EPwm5Regs.ETPS.bit.INTPRD = 1;     // Genera int despues del primer evento

	    asm(" EALLOW");                       // Enable EALLOW protected register access

	    PieCtrlRegs.PIEIER3.bit.INTx5 = 1;    // Habilita INT del PWM6 del grupo 3

	    EPwm5Regs.ETSEL.bit.INTSEL =0x1;      // Interrupcion cuando el contador es cero
	    EPwm5Regs.ETSEL.bit.INTEN = 1;        // Habilita interrupcion
	    EPwm5Regs.TBCTR = 0x0000;             // Clear timer counter Included by SIR

	//    PieCtrlRegs.PIEIER3.all =  0xFFFF;
	//    PieCtrlRegs.PIEIER4.all =  0xFFFF;
	    PieCtrlRegs.PIEACK.all = 0x0000;      // Enable PIE interrupts
	    IER |= 0x00FF;                              // Enable INT1 in IER to enable PIE group

	    asm(" EDIS");                         // Disable EALLOW protected register access
	 //********************************

    EPwm6Regs.TBCTR = 0x0000;                 // Clear timer counter Included by SIR

	// Run Time (Note: Example execution of one run-time instant)
	//===========================================================
	EPwm3Regs.CMPA.half.CMPA = 100; // adjust duty for output EPWM1A
	EPwm4Regs.CMPA.half.CMPA = 100; // adjust duty for output EPWM2A
	EPwm5Regs.CMPA.half.CMPA = 30; // adjust duty for output EPWM3A

    EPwm3Regs.ETCLR.bit.INT = 1;                  // Limpia bandera de interrupcion
    EPwm4Regs.ETCLR.bit.INT = 1;                  // Limpia bandera de interrupcion
    EPwm5Regs.ETCLR.bit.INT = 1;                  // Limpia bandera de interrupcion
//    IFR &=0xFFE3;

	//---------------------------------------------------------------------
	//--- Enable the clocks to the ePWM module.
	//--- Note: this should be done after all ePWM modules are configured
	//--- to ensure synchronization between the ePWM modules.
	//---------------------------------------------------------------------
	    asm(" EALLOW");                         // Enable EALLOW protected register access
	    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;  // TBCLK to ePWM modules enabled
	    asm(" EDIS");                           // Disable EALLOW protected register access



} // end InitEPwm()

EINT;                               // Habilita interrupciones del CPU
ERTM;                               // Habilita interrupciones en tiempo real del debugger

//--- end of file -----------------------------------------------------

0 Subrahmanya over 7 years ago in reply to S.Ibarra

TI__Mastermind 24095 points

Hi,

Your configuration at EPWM and PIE seems to be correct.
I'm wondering if the interrupt is not getting serviced because of the other higher priority interrupts.

For the purpose of debug,
Can you disable all other interrupts and only enable the EPWM5 interrupt and check that the interrupt is serviced?
If it's serviced, then it means that some other higher priority interrupt is not letting the EPWM5 to be serviced in your original code.

0 S.Ibarra over 7 years ago in reply to Subrahmanya

Intellectual 655 points

Hi Bharathi

I did the exercise of disable the epwmx interrupts:
Test 1: disabling the epwm3 and epwm4 interrupts, the result is that the epwm5 interrupt is generate.
Test 2: disabling the epwm3 interrupt, the result is that epwm4 and epwm5 interrupts was generate.
Test 3: disabling the epwm4 interrupt, the result is that epwm3 and epwm5 interrupts was generate.

Now, what I can do? I need construct the inverter in this week.

Thanks a lot.

Sebastián

0 Subrahmanya over 7 years ago in reply to S.Ibarra

TI__Mastermind 24095 points

Hi,

That's good - so, it's due to the interrupt of EPWM5 not getting time for execution.
What you can do, is enable nesting of the interrupts so that EPWM5 ISR can be executed by interrupting the other interrupt ISRs.
processors.wiki.ti.com/.../Interrupt_Nesting_on_C28x
Please go through the above link for interrupt nesting details.
Ideally, you should optimize the number of interrupts and try to see if the code can be executed from within one ISR for inverter control.

-Bharathi.

0 S.Ibarra over 7 years ago in reply to Subrahmanya

Intellectual 655 points

Hi Bharathi

I am using 30kHz of frecuency in the pwm modules and I need that the pwm modules generate 500 interrupts per each cycle of 60 Hz. I consider that the microcontroller frecuency (60MHz) is enough to manage this operation conditions.

Excuseme, I can modify the set up clocking to avoid the issue over interrupts priority?

Sebastián

0 S.Ibarra over 7 years ago in reply to Subrahmanya

Intellectual 655 points

Hi Bharathi

In my code the ADC1_INT was enabled, so I disabled the ADC1_INT then the epw3, epw4 and epwm5 generate the interrups. In this moment I don´t need the ADC interrupts. But when I will need the others peripherals, what it will happend?

I´m worried, because need use almost all peripherals in my project.

Sebastián

0 Subrahmanya over 7 years ago in reply to S.Ibarra

TI__Mastermind 24095 points

Hi

If you need only 500 interrupts in 60Hz and your PWM switching freq. is 30KHz - why do you need to enable so many interrupts?

Nevertheless, you can still address the interrupts by as you wish by the link i sent earlier
processors.wiki.ti.com/.../Interrupt_Nesting_on_C28x

-Bharathi.

0 Subrahmanya over 7 years ago in reply to S.Ibarra

TI__Mastermind 24095 points

I'm not sure I understand your concern here. You can use all the peripherals and take interrupts.
You can choose to combine certain interrupts or enable interrupt nesting, if you wish to let other interrupts to interrupt the current ISR.
Maximum number of interrupts, that can be serviced, also CPU utilization i.e. your ISR code as well.
So, it's totally up to the application.

0 S.Ibarra over 7 years ago in reply to Subrahmanya

Intellectual 655 points

Hi Bharathi

The ISR of epm´s is where I change of pulse width. While more pulses better is the sinusoidal produced and more easy will be filtering.

I think that the frequency fo the epwm´s is low, considering that the microcontroller can operate to 60MHz. Sincerely I did not expecting in this moment of my application overlap of interrupts. It is possible that I need to review the clock configuration to obtain better results.

Thanks a lot

Sebastián

0 Subrahmanya over 7 years ago in reply to S.Ibarra

TI__Mastermind 24095 points

Hi,

You can still use a single ISR to update all the PWM pulse width values. Please refer to any of the motor/inverter kit based example s/w on ControlSuite.

-Bharathi.

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CCS/TMS320F28035: Issue with epwm interrupt