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TMS320F280049C: ADC Module Synchronous Operation

SRW
Intellectual 370 points
Part Number: TMS320F280049C

I am looking at the technical reference manual for TMS320F28004x Piccolo Microcontrollers (Literature Number: SPRUI33A).

Referring to 13.3.1 Ensuring Synchronous Operation, which states "For best performance, all ADCs on the device should be operated synchronously. The device datasheet specifies the performance in both synchronous and asynchronous mode for those parameters which differ between the modes of operation."

1. Referring to the datasheet for "TMS320F28004x Piccolo™ Microcontrollers," Table 5-43. ADC Characteristics, Parameter "ADC-to-ADC Isolation" and "ENOB" show "Not Supported" for Asynchronous ADCs. So it would seem to me that this isn't really a suggestion, but rather a requirement as operating in this mode is undefined. Please confirm.

2. So I can better understand what is going on, can you please explain further why asynchronous mode is not supported, why the hardware as this limitation. The datasheet says "Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple ADCs." This lead me to believe I could just use each module however I see fit. Instead it seems I must pay very careful attention to how they are operated with respect to one another.

3. Lastly, just to confirm my understanding with a example application. Let's say ADC-A is operating SOC0-SOC3 at a predetermined interval for SMPS control. ADC-B SOC0 is triggered asynchronously, by an external device flagging an interrupt that a voltage needs to be sampled immediately. Therefore it is possible ADC-B SOC0 can be triggered to overlap ADC-A SOC1-3 and violate the Synchronous Operation requirement. The workaround that comes to mind would be, in the interrupt, to schedule the ADC-B SOC0 to synchronize with ADC-A SOC0, but this would potentially add a delay and defeat the purpose of using the interrupt in the first place. Am I understanding this correctly? This limits ADC operation but I don't want inaccurate results.

Thank you very much!

  • 0
    TI__Mastermind 28275 points

    Hi SRW,

    1. Referring to the datasheet for "TMS320F28004x Piccolo™ Microcontrollers," Table 5-43. ADC Characteristics, Parameter "ADC-to-ADC Isolation" and "ENOB" show "Not Supported" for Asynchronous ADCs. So it would seem to me that this isn't really a suggestion, but rather a requirement as operating in this mode is undefined. Please confirm.

    Yes, it's a requirement for best performance.

    2. So I can better understand what is going on, can you please explain further why asynchronous mode is not supported, why the hardware as this limitation. The datasheet says "Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple ADCs." This lead me to believe I could just use each module however I see fit. Instead it seems I must pay very careful attention to how they are operated with respect to one another.

    The ADCs are independent even though some packages share some components like reference etc. Because all the ADCs are close together on the chip, activity on one can affect the other which is why for best performance, they shouldn't be operated asynchronously. Synchronous operation doesn't necessarily mean the ADCs can't be operated independently. For best performance, you have two options, either synchronize the ADCs or make sure the sampling+conversion phase of one ADC does not overlap the other.

    3. Lastly, just to confirm my understanding with a example application. Let's say ADC-A is operating SOC0-SOC3 at a predetermined interval for SMPS control. ADC-B SOC0 is triggered asynchronously, by an external device flagging an interrupt that a voltage needs to be sampled immediately. Therefore it is possible ADC-B SOC0 can be triggered to overlap ADC-A SOC1-3 and violate the Synchronous Operation requirement. The workaround that comes to mind would be, in the interrupt, to schedule the ADC-B SOC0 to synchronize with ADC-A SOC0, but this would potentially add a delay and defeat the purpose of using the interrupt in the first place. Am I understanding this correctly? This limits ADC operation but I don't want inaccurate results.

    If the set of SOCs across ADCs have different triggers, then by definition they can't be guaranteed to be synchronous. From your example, ADCASOC0 and ADCBSOC0 have different triggers so they can't be guaranteed synchronous operation.

  • 0 in reply to Frank Ankapong
    Intellectual 370 points
    Thank you Frank.
  • 0 in reply to SRW
    TI__Mastermind 28275 points
    Glad i could help. Let us know if you have anymore questions.
  • 0 in reply to Frank Ankapong
    Intellectual 370 points
    Actually, just noticed another thing, just checking my understanding here. The features list for this part shows "Ratiometric external reference set by VREFHI/VREFLO."

    In the TRM, section 13.1.3.2.1 External Reference Mode, says "Each ADC has a VREFHI input and a VREFLO input, which is used as a ratiometric reference.
    • Consult the datasheet for your device to determine the allowable voltage range for VREFHI and VREFLO."

    The datasheet says VREFLO has to be tied to VSSA, in other words, 0V. I don't understand why there is hinting as some sort of flexibility to VREFLO when in fact it must remain at VSSA in all cases. Given the wording in the TRM, this is not the ratiometric operation I was expecting. I was expecting VREFLO to be allowed to be biased up, for example to 1.65V. This way more resolution can be measured for signals in the range of 1.65V to 3.3V. But instead it is only VREFHI that can be adjusted down.

    Please confirm if my understanding is correct.

    That being said, I do recognize this ADC module has a lot of capabilities, which may provide workarounds to VREFLO being fixed to VSSA.

    Thanks again for the speedy and thorough responses, Frank.
  • 0 in reply to SRW
    TI__Mastermind 28275 points
    SRW,

    The TRM is usually written to be a bit generic which is why there are multiple statements about checking the datasheet for the actual specification. With that said, i agree that the wording could be a bit better. If you want more resolution (in terms of volts), you can decrease VREFHI to 2.4V. If your signal is in the range of 1.65V to 3.3V, you can offset it to fit into 2.4V.
  • 0 in reply to SRW
    TI__Mastermind 28275 points
    SRW,

    Did the answer clear it up for you?
  • 0 in reply to Frank Ankapong
    Intellectual 370 points

    Yes thank you.

  • 0 in reply to SRW
    TI__Mastermind 28275 points
    Awesome. Let us know if you have any more questions.