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TMS320F28035: Trip zone takes too much time to carried out trip action on PWM

Daniel_EE
Intellectual 670 points
Part Number: TMS320F28035


HI, 

How long trip zone will take to carry out the mentioned action on ePWM? 

Is the trip zone logically anded with PWM out?

 

  • 0
    Guru 192875 points

    Hi Daniel,

    Daniel_EE said:
    How long trip zone will take to carry out the mentioned action on ePWM? 

    A minimum of 3*TBCLK low pulse width on TZn inputs is sufficient to trigger a fault condition on the ePWM module. Check the ePWM user-guide.

    How much time does it take on your end?

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Intellectual 670 points
    I see 300nsecs which way more than what you have said. I also disabled the action qualifier on trip pin but that didn't help.
    What else could be the reason?
    Trip pin is directly connected to the microcontroller wihtout any filter in between them.
  • 0 in reply to Daniel_EE
    TI__Mastermind 42195 points

    Daniel,

    could you include a scope capture? I'm expecting something closer to 2 cycles +20 nS.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 670 points

    The Q1 is the PWM.

    Dark yellow U224 is the trip signal, which goes low first. after 220nsec PWM goes low.

    Which is way too much. Trip is directly connected to the 28035. PWM is configured to go low on trip event. 

  • 0 in reply to Daniel_EE
    TI__Guru 57255 points

    Hi,

    It looks like you are using an external analog comparator to generate a trip signal.  That signal, TRIPU23 (dark yellow), would to go into a GPIO.  And this GPIO is configured as a TZ.  Assuming so, then you should be able to get a trip response of around 25ns.
     
    1) Your PWM pin looks like it has a significant amount of capacitance on it.  I'm not to worried about this, however it may be worthwhile at some point to move to a simpler system like a TI EVM to prove out trip zone functionality & your configuration.  Once you get things working, you could then move back to your custom board.  This is how I typically work with the TZ submodule until I've gained confidence in my configuration.

    2) I would recommend confirming that the TZ GPIO input is configured to have asynchronous qualification.

    3) If the above (& more of your debug doesn't help), I might recommend posting your TZ.configuration code.


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Intellectual 670 points
    Tried all the option you sugested. Did not get any improvement.

    My trip zone configuration is as below.

    // GPIO-12 - PIN FUNCTION = TZ1
    GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // 0=GPIO, 1=TZ1, 2=SCITX-A, 3=SPISIMO-B
    GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3;


    void HVDMCProtection(void)
    {

    // Configure Trip Mechanism for the Motor control software
    // -Cycle by cycle trip on CPU halt
    // -One shot IPM trip zone trip
    // These trips need to be repeated for EPWM1 ,2 & 3

    //===========================================================================
    //Motor Control Trip Config, EPwm1,2,3
    //===========================================================================
    EALLOW;
    // CPU Halt Trip
    EPwm1Regs.TZSEL.bit.CBC1 = 0x1;
    EPwm2Regs.TZSEL.bit.CBC1 = 0x1;
    EPwm3Regs.TZSEL.bit.CBC1 = 0x1;

    // What do we want the OST/CBC events to do?
    // TZA events can force EPWMxA
    // TZB events can force EPWMxB

    EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
    EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low

    EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
    EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low

    EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
    EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low

    EPwm1Regs.TZEINT.bit.CBC = 1;
    // EPwm2Regs.TZEINT.bit.CBC = 1;
    // EPwm3Regs.TZEINT.bit.CBC = 1;
    EDIS;

    // enable trip zone interrupts in the pie
    PieCtrlRegs.PIEIER2.bit.INTx1 = 1;
    IER |= M_INT2;
    IER |= M_INT3;

    // Clear any spurious OV trip
    EPwm1Regs.TZCLR.bit.CBC = 1;
    EPwm2Regs.TZCLR.bit.CBC = 1;
    EPwm3Regs.TZCLR.bit.CBC = 1;

    EALLOW;
    // This is needed to write to EALLOW protected registers
    PieVectTable.EPWM1_TZINT = &Epwm1TZISR;
    EDIS;
    // This is needed to disable write to EALLOW protected registers

    //************************** End of Prot. Conf. ***************************//
    }
  • 0 in reply to Daniel_EE
    TI__Guru 57255 points

    A few notes:

    Make sure that  your qualification selection register write is within an EALLOW/EDIS block.  You can also double-check that the register write is taking place by confirming in the expressions window.  You should be able to see the latency of trip change with different settings.

    Can you also confirm that the measured signal 'Q2' is the signal at the C2000 pin, not after something like a gate driver?

    Outside of the potential concern with EALLOW with QSEL, your code seems reasonable. 

    FYI: I would recommend writing to all valid register bits in the TZCTL register.  Specifically configure the DCxEVTn events to Do-Nothing.  I don't believe this will affect what you are seeing, but can save some potential debug headaches.


    Thank you,
    Brett