CCS/TMS320F28377D: Initialized variables in CPU2 code are not getting initialized at startup

Zubair Hameed

Part Number: TMS320F28377D

Tool/software: Code Composer Studio

Hello

I am using linker cmd files as attached for CPU1 and CPU2 cores. I am assigning CPU2 as master for GS8 to GS15 RAM sections during the CPU1 initialization code using GSxMSEL register per the technical manual. On CPU2 startup, the CPU2 can read/write global variables but the initialized global variables are not getting initialized at startup (these are all 0's). If If I do not use GSx RAM for CPU2, all the gloabl initialized variables in CPU2 are getting initialized properly.

Any help will be greatly appreciated.

Zubair Hameed

Fullscreen project_address_space_cpu2.txt Download

/*
 *---------------------------------------------------------------------------
 *   GE AVIATION SYSTEMS LLC PROPRIETARY INFORMATION
 *---------------------------------------------------------------------------
 *
 *   The information contained in this document is GE Aviation Systems LLC
 *   proprietary information and is disclosed in confidence.  It is the
 *   property of GE Aviation Systems LLC and shall not be used, disclosed to
 *   others or reproduced without the express written consent of GE Aviation
 *   Systems LLC, including, but without limitation, it is not to be used in
 *   the creation, manufacture, development, or derivation of any repairs,
 *   modifications, spare parts, designs, or configuration changes or to
 *   obtain FAA or any other government regulatory approval to do so. If
 *   consent is given for reproduction in whole or in part, this notice shall
 *   appear in any such reproduction in whole or in part.
 *
 *   This technical data is considered ITAR and/or EAR controlled pursuant to
 *   22 CFR Part 120-130 and 15 CFR Parts 730-774 respectively.  Transfer of
 *   this data by any means to a Non-US Person, whether in the United States
 *   or abroad, without the proper U.S. Government authorization
 *   (e.g., License, exemption, NLR, etc.), is strictly prohibited.
 *
 *   Copyright 2015 GE AVIATION SYSTEMS LLC, U.S.A.
 *---------------------------------------------------------------------------
 */

/*
 * project_address_space.cmd - This linker command file defines the address locations
 *                             for the main project.
 */

MEMORY
{
PAGE 0 :                                                   /* Program Memory */
                                                           /* OFP_BEGIN is the entry point of the program */
    RESET           : origin = 0x3FFFC0, length = 0x000002

  	STACK			: origin = 0x000000, length = 0x000400 /* M0_RAM, Size = 1k  */
   	M1_RAM          : origin = 0x000400, length = 0x000400 /* M1-RAM, Size = 1k -- available */

	/* RAM Functions:  EC Control Code, Flash initialization code
	   RAM sections: LS0 to LS5 and D0.  Total Size = 14k */
   	RAM_FUNCS		: origin = 0x008000, length = 0x003800

   	/* Scratch pad for RAM test. RAM section = D1. Size = 2k */
   	SCRATCH_PAD     : origin = 0x00B800, length = 0x000800

	/* Exciter Control RAM sections (CPU1): GS0 to GS7. Size = 32k */
    EC_RAM          : origin = 0x00C000, length = 0x008000
    /* Main Control RAM sections (CPU2): GS8 to GS15. Size = 32k */
    MC_RAM          : origin = 0x014000, length = 0x008000

/* Flash Sectors */
   	OFP_BEGIN       : origin = 0x080000, length = 0x000002 /* CODESTART (OFP)  */
   	FLASH_RELOCATE  : origin = 0x080002, length = 0x003800 /* EC Control Code and RAM initialization function = 14k */
   	OFP             : origin = 0x083802, length = 0x03C7FD /* All remaining Flash allocated to OFP */

PAGE 1:

   	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   	CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}

SECTIONS
{
  	.cinit          : > MC_RAM			PAGE = 0, ALIGN(4) /* Initialized C variables */
  	.pinit			: > MC_RAM         PAGE = 0, ALIGN(4)
  	.text           : > OFP         PAGE = 0, ALIGN(4)

  	codestart       : > OFP_BEGIN   PAGE = 0, ALIGN(4)

   	ramfuncs        : LOAD = FLASH_RELOCATE,
                      RUN = RAM_FUNCS,
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)

	/* Allocate uninitalized data sections: */
   	.stack			: > STACK      PAGE = 0
   	.ebss           : > MC_RAM     PAGE = 0
   	.data           : > MC_RAM     PAGE = 0
//   	.ebss:SCRATCH   : > Dx_RAM      PAGE = 0

    /* Initalized sections go in Flash */
   	.econst         : > OFP        	PAGE = 0, ALIGN(4)
   	.switch         : > OFP        	PAGE = 0, ALIGN(4)

   	.reset          : > RESET,     	PAGE = 0, TYPE = DSECT

/* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }
}

/*=========================================================================== */
/* End of file.                                                               */
/*=========================================================================== */

Fullscreen project_address_space_cpu1.txt Download

/*
 *---------------------------------------------------------------------------
 *   GE AVIATION SYSTEMS LLC PROPRIETARY INFORMATION
 *---------------------------------------------------------------------------
 *
 *   The information contained in this document is GE Aviation Systems LLC
 *   proprietary information and is disclosed in confidence.  It is the
 *   property of GE Aviation Systems LLC and shall not be used, disclosed to
 *   others or reproduced without the express written consent of GE Aviation
 *   Systems LLC, including, but without limitation, it is not to be used in
 *   the creation, manufacture, development, or derivation of any repairs,
 *   modifications, spare parts, designs, or configuration changes or to
 *   obtain FAA or any other government regulatory approval to do so. If
 *   consent is given for reproduction in whole or in part, this notice shall
 *   appear in any such reproduction in whole or in part.
 *
 *   This technical data is considered ITAR and/or EAR controlled pursuant to
 *   22 CFR Part 120-130 and 15 CFR Parts 730-774 respectively.  Transfer of
 *   this data by any means to a Non-US Person, whether in the United States
 *   or abroad, without the proper U.S. Government authorization
 *   (e.g., License, exemption, NLR, etc.), is strictly prohibited.
 *
 *   Copyright 2015 GE AVIATION SYSTEMS LLC, U.S.A.
 *---------------------------------------------------------------------------
 */

/*
 * project_address_space.cmd - This linker command file defines the address locations
 *                             for the Exciter Control project.
 */

MEMORY
{
PAGE 0 :

	RESET			: origin = 0x3FFFC0, length = 0x000002

   	/* Note: "length" below is specified in words */

   	STACK			: origin = 0x000000, length = 0x000400 /* M0_RAM, Size = 1k  */
   	M1_RAM          : origin = 0x000400, length = 0x000400 /* M1-RAM, Size = 1k -- available */

	/* RAM Functions:  EC Control Code, Flash initialization code
	   RAM sections: LS0 to LS5 and D0.  Total Size = 14k */
   	RAM_FUNCS		: origin = 0x008000, length = 0x003800

   	/* Scratch pad for RAM test. RAM section = D1. Size = 2k */
   	SCRATCH_PAD     : origin = 0x00B800, length = 0x000800

	/* Exciter Control RAM sections (CPU1): GS0 to GS7. Size = 32k */
    EC_RAM          : origin = 0x00C000, length = 0x008000
    /* Main Control RAM sections (CPU2): GS8 to GS15. Size = 32k */
    MC_RAM          : origin = 0x014000, length = 0x008000

/* Flash Sectors */
   	OFP_BEGIN       : origin = 0x080000, length = 0x000002 /* CODESTART (OFP)  */
   	FLASH_RELOCATE  : origin = 0x080002, length = 0x003800 /* EC Control Code and RAM initialization function = 14k */
   	OFP             : origin = 0x083802, length = 0x03C7FD /* All remaining Flash allocated to OFP */

PAGE 1:

   	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   	CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}

SECTIONS
{
  	.cinit          : > OFP			PAGE = 0, ALIGN(4) /* Initialized C variables */
  	.pinit			: > OFP         PAGE = 0, ALIGN(4)
  	.text           : > OFP         PAGE = 0, ALIGN(4)

  	codestart       : > OFP_BEGIN   PAGE = 0, ALIGN(4)

   	ramfuncs        : LOAD = FLASH_RELOCATE,
                      RUN = RAM_FUNCS,
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)

	/* Allocate uninitalized data sections: */
   	.stack			: > STACK      PAGE = 0
   	.ebss           : > EC_RAM     PAGE = 0
   	.data           : > EC_RAM     PAGE = 0
//   	.ebss:SCRATCH   : > Dx_RAM      PAGE = 0

    /* Initalized sections go in Flash */
   	.econst         : > OFP        	PAGE = 0, ALIGN(4)
   	.switch         : > OFP        	PAGE = 0, ALIGN(4)

   	.reset          : > RESET,     	PAGE = 0, TYPE = DSECT

 /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }
}

over 7 years ago

0 Sal Pezzino over 7 years ago

TI__Mastermind 32995 points

Hi Zubair,

Are you assigning the GS RAMs to CPU2 before booting CPU2? How are you booting CPU2 from CPU1?

If CPU2 owns those GS RAMs before it begins executing c_int00 then it should work.

Regards,
sal

0 Zubair Hameed over 7 years ago in reply to Sal Pezzino

Prodigy 190 points

I am assigning GS RAMs to CPU2 in CPU1 code after the main() is called and all CPU1 clocks are initialized. I am booting CPU2 from CPU1 by using the IPC Boot Mode command C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH in the CPU1 code well after GS RAMs are assigned to CPU2.

I am testing this with debugger by loading cpu1 and cpu2 codes, starting the cpu1 execution, and then starting cpu2 execution.

Follow up question: Does the c_int00 is executed when binary image is loaded in debugger but not started? If answer is yes, then this explains why cpu2 code initialized variables are not getting initialized. Is there a work around so that c_int00 is not executed on loading the binary file in debugger?

Zubair

0 Sal Pezzino over 7 years ago in reply to Zubair Hameed

TI__Mastermind 32995 points

Hi Zubair,

Yes. When you load symbols to a target CPU, the debugger will execute c_int00 and then break or stop at main().

1) If you run your application from standalone it should work.
2) If you connect and load CPU1 and run the code to give CPU2 access to the GS RAM, and then connect and load CPU2, the it should work as well.

Regards,
sal

0 Vivek Singh over 7 years ago in reply to Sal Pezzino

TI__Guru** 115881 points

Also other option is to uncheck the default setting of "RUN to symbol Main" option in CCS (uncheck the so that c_int00 function does not run after code is loaded on CPU2.

Regards,

Vivek Singh

0 Zubair Hameed over 7 years ago in reply to Vivek Singh

Prodigy 190 points

This solves my issue. Thank you very much for your help.
Regards
Zubair Hameed

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CCS/TMS320F28377D: Initialized variables in CPU2 code are not getting initialized at startup