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TMS320F28379D: Changing pwm configuration in ISR.

Aditya Ghule
Intellectual 260 points
Part Number: TMS320F28379D

Hi,

I am trying to change the configuration of ePWM Action Qualifier Control Registers in between a code execution.  Here is the setup:

10kHz interrupt frequency ( 100us time period).  My average computation time is about 10us.

Compare values are loaded in shadow mode at CTR = 0.

I basically need the new configuration and values to be executed at the start of the next CTR =0.  The shadow mode does this perfectly.

For updating the AQCTLA and AQCTLB I have two options.

a) Update the configuration at the end of computations.  This makes sure that the correct configuration is available for the next CTR =0.  However the incorrect configuration is updated for the one cycle till the CTR =0 which might cause problems.

b) Update the configuration at the beginning of the next interrupt.  By this the correct configuration is updated just past CTR =0.  This has incorrect pwm behavior only till the next compare event is reached.  However it still might cause problems if the compare event happens before the configuration gets changed.

I was wondering if there is a better approach for this implementation.

Thank you,

Aditya Ghule

  • 0
    TI__Guru 52040 points

    Why not use shadow mode for AQCTL ?

    Here is the section on how to set this up. This way you dont have to manually update the AQCTL at the exact correct time.

    14.6.4 AQCTLA and AQCTLB Shadow Mode Operations

    To enable Action Qualifier mode changes which must occur at the end of a period even when the phase changes, shadowing of the AQCTLA and AQCTLB registers has been added on ePWMs type 2 and later. Additionally, shadow to active load on SYNC of these registers is supported as well. Shadowing of this register is enabled and disabled by the AQCTLR[SHDWAQAMODE] and AQCTLR[SHDWAQBMODE] bits. These bits enable and disable the AQCTLA shadow register and AQCTLB shadow register, respectively. The behavior of the two load modes is described below: Shadow Mode: The shadow mode for the AQCTLA is enabled by setting the AQCTLR[SHDWAQAMODE] bit, and the shadow register for AQCTLB is enabled by setting the AQCTLR[SHDWAQBMODE] bit. Shadow mode is disabled by default for both AQCTLA and AQCTLB If the shadow register is enabled, then the content of the shadow register is transferred to the active register on one of the following events as specified by the AQCTLR[LDAQAMODE] AQCTLR[LDAQBMODE] AQCTLR[LDAQASYNC] & AQCTLR[LDAQBSYNC] register bits:

    • CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).

    • CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)

    • Both CTR = PRD and CTR = Zero

    • SYNC event caused by DCAEVT1 or DCBEVT1 or EPWMxSYNCI or TBCTL[SWFSYNC]

    • Both SYNC event or a selection made by LDAQAMODE/LDAQBMODE

    Global Load Support Global load control mechanism can also be used for AQCTLA:AQCTLA2, AQCTLB:AQCTLB2 and AQCSFRC registers by configuring the appropriate bits in the global load configuration register (GLDCFG). When global load mode is selected, the transfer of contents from shadow register to active register for all registers that have this mode enabled, occurs at the same event as defined by the configuration bits in the Global Shadow to Active Load Control Register (GLDCTL). The global load control mechanism is explained in Section

    14.4.7. Immediate Load Mode: If immediate load mode is selected (that is, AQCTLR[SHDWAQAMODE] = 0 or AQCTLR[SHDWAQBMODE] = 0), then a read from or a write to the register will go directly to the active register. See Figure 14-22 and Figure 14-23.

    Also you can always use Global load. But thats your choice.

  • 0 in reply to Nima Eskandari
    Intellectual 260 points
    Thanks for the suggestion. I did not realize that there was a shadow register for the configuration too. I was able to use the AQCTLR Shadow mode to synchronize the configuration and the compare value to ctr =zero.