TMS320F280049: Unexpect PWM output by using CMPSS to provide the T1/T2 event

Brian Chang90901

Intellectual 2540 points

Part Number: TMS320F280049

Dear C2000 expert

We are trying to use CMPSS to provide CTRIP signal in order to generate the T1 /T2 event.

The CTRIPH was selected as CTRIP_FILTER

Generally the output was look good.The 2A/2B was turn on / turn off at the T1 event (T1D/ T1U)

When we put the configuration at close loop to do PSFB control , we fund the 2A/2B signal was shoot through.

We look at the EPWM open loop and we fund such wrong was impacted by CTRIP signal waveform.

The B channel wil work not correctly and get crasy.

We try to simplize the issue. We set PWMA and PWMB channel was all the same configuration and the dead time set to zero.

We the the PWMB signal was becoming uncontrollable when the T1 event was triggered.

PWMB was change the state after the CTRIP sinal was low. We also fund the PWM module was getting uncontrollable until we disable the T1 event.

I didnot know why the PWMB signal become unexpected waveform.

We also find the strange behavior when we try to change the OUTSWAP(DB module) to verify the PWMA and PWMB at this kind of condition.

The OUTSWAP( DB module) was not follow the value we changed until we disable the T1 event source.

So , we would like ask

1. the DC sub moulde was level trigger or edge trigger?

2. What was the potential issue to affect the ePWM module as this condition??

Thanks

Brian

over 7 years ago

0 Subrahmanya over 7 years ago

TI__Mastermind 24095 points

Hi Brian, can you please share your ePWM configuration code? I've to know How the DC event is configured/generated and how PWM is configured using T1/T2.

0 Brian Chang90901 over 7 years ago in reply to Subrahmanya

TI__Intellectual 2540 points

Hi ,

please see the attachment with fulll code and CMPSS / PWM configuration file as bellowing

Full code

F280049_PSFB.zip

PWM / CMPSS configuration

Fullscreen PSFB_PWM_CNF.c Download

//----------------------------------------------------------------------------------
//	FILE:			HVPSFB-Main.C
//
//	Description:	Peak current mode control of a phase shifted full bridge
//
//	Version: 		1.0
//
//  Target:  		TMS320F28004x Protenza
//
//----------------------------------------------------------------------------------
//  Copyright Texas Instruments 2004-2009
//----------------------------------------------------------------------------------
//  Revision History:
//----------------------------------------------------------------------------------
//  Date	  | Description / Status
//----------------------------------------------------------------------------------
// 18 Apr 2011 - Peak Current Mode Controlled Phase Shifted Full bridge (HN)
// 03 March 2016 - Modify code structure and definition (BC)
// 30 May   2016 - Add git function
// 14 June  2018 - Modify the file for F280049
// 22 June  2018 - add test mode for PWM scheme
//----------------------------------------------------------------------------------

#include "HVPSFB-Settings.h"


//#include "DSP2803x_EPWM_defines.h"

#include "HVPSFB-CLAShared.h"
#include "SFRA_IQ_Include.h"

#include "IQmathLib.h"
#include "global_variable.h"
#include "PSFB_PowerCtrl.h"
#include "DPlib.h"
#include "statemachine.h"
#include "f28004x_epwm_defines.h"

#define LAG_PWM_DT	60	// 60*10 ns = 600ns
#define LEAD_PWM_DT 60 	// 60*10 ns = 600ns
#define SR_DT		60	// 60*10 ns = 600ns



//*******************************************************************************
// function : PSFB_PWM_CNF
// Description:  Configure the PSFB PWM mode
//*******************************************************************************
void PSFB_PWM_CNF(int PRD)
{
	// turn off PWM pin by configure as GPIO
	EALLOW;
	GpioDataRegs.GPADAT.bit.GPIO0 = 0;
	GpioDataRegs.GPADAT.bit.GPIO1 = 0;
	GpioDataRegs.GPADAT.bit.GPIO2 = 0;
	GpioDataRegs.GPADAT.bit.GPIO3 = 0;
	GpioDataRegs.GPADAT.bit.GPIO4 = 0;
	GpioDataRegs.GPADAT.bit.GPIO5 = 0;

	GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0;
	GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0;
	GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0;
	GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0;
	GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0;
	GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0;

	GpioCtrlRegs.GPADIR.bit.GPIO0 =1;
	GpioCtrlRegs.GPADIR.bit.GPIO1 =1;
	GpioCtrlRegs.GPADIR.bit.GPIO2 =1;
	GpioCtrlRegs.GPADIR.bit.GPIO3 =1;
	GpioCtrlRegs.GPADIR.bit.GPIO4 =1;
	GpioCtrlRegs.GPADIR.bit.GPIO5 =1;
	EDIS;


	// PWM initialization
	InitEPwm1Example(PRD);
	InitEPwm2Example(PRD);
	InitEPwm3Example(PRD);
	InitEPwm4Example(PRD);

	// enable the SOC for ADC sampling
    EPwm1Regs.ETSEL.bit.SOCAEN = 1;     // Disable SOC on A group
    EPwm1Regs.ETSEL.bit.SOCASEL = 1;    // Select SOC on ZREO
    EPwm1Regs.ETPS.bit.SOCAPRD = 1;     // Generate pulse on 1st event

    EPwm1Regs.ETSEL.bit.SOCBEN = 1;     // Disable SOC on A group
    EPwm1Regs.ETSEL.bit.SOCBSEL = 2;    // Select SOC on PERIOD
    EPwm1Regs.ETPS.bit.SOCBPRD = 1;     // Generate pulse on 1st event
#if 0
	// enable the pin for PSFB Control
	EALLOW;
	GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;
	GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;
	GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;
	GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;
	GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;
	GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;
	EDIS;
#endif

	EALLOW;
	//Configure TRIP4 to be CTRIP1H
	EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0;
	//Enable TRIP4 Mux for Output
	EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0   = 1;
	// inputXbar1
	EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX1 = 1;
	//Enable TRIP4 Mux for Output
	EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX1   = 1;
	EDIS;

	// Configure GPIO15 to output CTRIP1H/EPWM TRIP4
	//GPIO_SetupPinMux(   GPIO_CTRIP_PIN_NUM, GPIO_MUX_CPU1,    GPIO_CTRIP_PER_NUM);
	// Configure GPIO14 to output CTRIPOUT1H
	//GPIO_SetupPinMux(GPIO_CTRIPOUT_PIN_NUM, GPIO_MUX_CPU1, GPIO_CTRIPOUT_PER_NUM);

}

//*******************************************************************************
// function : PSFB_PCMC_Config
// Description:  Configure the  CMPSS for peak current mode control
//*******************************************************************************
void PSFB_PCMC_Config(void)
{
		EALLOW;
	    //Enable CMPSS
	    Cmpss1Regs.COMPCTL.bit.COMPDACE            = 1;
	    //NEG signal comes from DAC
	    Cmpss1Regs.COMPCTL.bit.COMPHSOURCE         = NEGIN_DAC;
	    //Use VDDA as the reference for DAC
	    Cmpss1Regs.COMPDACCTL.bit.SELREF           = REFERENCE_VDDA;
	    //Set DAC to midpoint for arbitrary reference
	    Cmpss1Regs.DACHVALS.bit.DACVAL             = 2048;
	    //
	    Cmpss1Regs.COMPDACCTL.bit.RAMPSOURCE = 3;   // PWMSYN4
	    Cmpss1Regs.COMPDACCTL.bit.DACSOURCE  = 1;   // Ramp


	    Cmpss1Regs.COMPSTSCLR.bit.HSYNCCLREN  = 1;
	    //
	    Cmpss1Regs.RAMPMAXREFS = 16000;
	    Cmpss1Regs.RAMPDECVALS = 10;


	    Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 9;
	    Cmpss1Regs.CTRIPHFILCTL.bit.THRESH  = 5;
	    Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0;
	    // Configure CTRIPOUT path
	    //Asynch output feeds CTRIPH and CTRIPOUTH
	    //Cmpss1Regs.COMPCTL.bit.CTRIPHSEL           = CTRIP_ASYNCH;
	    //Cmpss1Regs.COMPCTL.bit.CTRIPHSEL           = CTRIP_FILTER;
	    Cmpss1Regs.COMPCTL.bit.CTRIPHSEL           = CTRIP_FILTER;		// modify it because fault condition happen
	    Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL        = CTRIP_FILTER;


	    Cmpss1Regs.COMPDACCTL.bit.BLANKSOURCE  = 3; // EPWM4
	    Cmpss1Regs.COMPDACCTL.bit.BLANKEN      = 1; // Enable Blanking window from EPWM

	    // Configure CTRIPOUTH output pin
	    //Configure OUTPUTXBAR3 to be CTRIPOUT1H
//	    OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 0;
//	    //Enable OUTPUTXBAR3 Mux for Output
//	    OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0   = 1;
	    EDIS;


		// DAC
		EALLOW;
		AnalogSubsysRegs.ANAREFCTL.bit.ANAREFA2P5SEL = 0;
		AnalogSubsysRegs.ANAREFCTL.bit.ANAREFASEL    = 0;
	    //Use VDAC as the reference for DAC
	    DacaRegs.DACCTL.bit.DACREFSEL  = REFERENCE_VDAC;
	    DacaRegs.DACCTL.bit.MODE 	   = 1;
	    //Enable DAC output
	    DacaRegs.DACOUTEN.bit.DACOUTEN = 1;
	    DacaRegs.DACVALS.all =  800;
	    EDIS;
}

//*******************************************************************************
// function : InitEPwm1Example
// Description:  Configure the  EPWM1 as Fixed ARM
//*******************************************************************************
void InitEPwm1Example(int PRD)
{

    // Setup TBCLK
    EPwm1Regs.TBPRD = PRD;          // Set timer period 801 TBCLKs
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                     // Clear counter

    // Set Compare values
    EPwm1Regs.CMPA.bit.CMPA = 0;    	// Set compare A value
    EPwm1Regs.CMPB.bit.CMPB = 0;    	// Set Compare B value

    // Setup counter mode
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;       // Disable phase loading
    EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;			  // SYNC at count to Zero
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;      // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    // Setup shadowing
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    // Set actions
    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;

    EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR;


    // dead time
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm1Regs.DBCTL.bit.IN_MODE  = DBA_RED_DBB_FED;
    EPwm1Regs.DBCTL.bit.POLSEL   = DB_ACTV_HIC;

    EPwm1Regs.DBFED.all = LAG_PWM_DT;
    EPwm1Regs.DBRED.all = LAG_PWM_DT;


    // Interrupt where we will change the Compare Values
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
    EPwm1Regs.ETSEL.bit.INTEN = 0;                // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event



}
//*******************************************************************************
// function : InitEPwm2Example
// Description:  Configure the  EPWM2 as Shift ARM
//*******************************************************************************
void InitEPwm2Example(int PRD)
{

    // Setup TBCLK
    EPwm2Regs.TBPRD = PRD;         // Set timer period 801 TBCLKs
    EPwm2Regs.TBPHS.bit.TBPHS = 2;          // Phase is 0
    EPwm2Regs.TBCTR = 0x0000;                    // Clear counter

    // Set Compare values
    EPwm2Regs.CMPA.bit.CMPA = PRD-1;    // Set compare A value
    EPwm2Regs.CMPB.bit.CMPB = 0;    // Set Compare B value

    // Setup counter mode
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm2Regs.TBCTL.bit.PHSEN = 1;       // Disable phase loading
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;      // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;


    // Setup shadowing
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;


    EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm2Regs.AQCTLA2.bit.T1D = AQ_SET;   // peak current mode
    EPwm2Regs.AQCTLA2.bit.T1U = AQ_CLEAR;
    EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;  // for duty limit or voltage mode
    EPwm2Regs.AQCTLA.bit.CBD = AQ_SET;    // for voltage mode , the duty limt should > than dead time
    EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;

    EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET;
    EPwm2Regs.AQCTLB.bit.CBD = AQ_SET;    // for duty limit or voltage mode
    EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;  // for voltage mode , the duty limit should > than dead time
    EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR;
    EPwm2Regs.AQCTLB2.bit.T1U = AQ_CLEAR;
    EPwm2Regs.AQCTLB2.bit.T1D = AQ_SET;




    // dead time
#if 1
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm2Regs.DBCTL.bit.IN_MODE  = DBA_RED_DBB_FED;
    EPwm2Regs.DBCTL.bit.POLSEL   = DB_ACTV_HIC;
    EPwm2Regs.DBCTL.bit.OUTSWAP  = 0x03;            // A: B-path  B: A-path


    EPwm2Regs.DBFED.all = LEAD_PWM_DT;
    EPwm2Regs.DBRED.all = LEAD_PWM_DT;
#else
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm2Regs.DBCTL.bit.IN_MODE  = DBA_RED_DBB_FED;
    EPwm2Regs.DBCTL.bit.POLSEL   = 0;
    EPwm2Regs.DBCTL.bit.OUTSWAP  = 3;            // A: B-path  B: A-path


    EPwm2Regs.DBFED.all = 0;
    EPwm2Regs.DBRED.all = 0
#endif



    EALLOW;

    EPwm2Regs.AQTSRCSEL.bit.T1SEL          = 3;// DCBEVT2 to be T1

    //Configure EPWM2B to output low on  TRIP
    //Configure DCB to be TRIP4
    EPwm2Regs.TZDCSEL.bit.DCBEVT2          = TZ_DCBH_HI;
    EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL    = 0xF; //DCBHTRIPSEL
    EPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT4   = 1;
    //Configure DCB as CBC
    EPwm2Regs.DCBCTL.bit.EVT2SRCSEL        = DC_EVT2;
    EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL    = DC_EVT_ASYNC;
    EPwm2Regs.TZCLR.bit.CBC                = 1;

    EPwm2Regs.DCFCTL.bit.PULSESEL = 0x10;
    EPwm2Regs.DCFCTL.bit.SRCSEL   = 0x11;
    EPwm2Regs.DCFWINDOW  = 0x60;
    EPwm2Regs.DCFCTL.bit.BLANKE   = 1;
    EDIS;


    // Interrupt where we will change the Compare Values
    EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;    // Select INT on Zero event
    EPwm2Regs.ETSEL.bit.INTEN = 0;               // disable INT
    EPwm2Regs.ETPS.bit.INTPRD = ET_3RD;          // Generate INT on 3rd event



}


//*******************************************************************************
// function : InitEPwm3Example
// Description:  Configure the  EPWM3 as SR PWM pin
//*******************************************************************************
void InitEPwm3Example(int PRD)
{


#if 1

    // Setup TBCLK
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up/down and down
    EPwm3Regs.TBPRD = PRD-1;           // Set timer period
    EPwm3Regs.TBCTL.bit.PHSEN = 1;        // Disable phase loading
    EPwm3Regs.TBPHS.bit.TBPHS = 2;            // Phase is 0
    EPwm3Regs.TBCTR = 0x0000;                      // Clear counter
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    // Setup shadow register load on ZERO
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    // Set Compare values
    EPwm3Regs.CMPA.bit.CMPA = PRD-2;   // Set compare A value
    EPwm3Regs.CMPB.bit.CMPB = 0;   // Set Compare B value
#if 0
    // Set Actions
    EPwm3Regs.AQCTLA.bit.PRD = AQ_SET;           // Set PWM3A on period
    EPwm3Regs.AQCTLA.bit.CBD = AQ_CLEAR;         // Clear PWM3A on event B, down
                                                 // count

    EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR;         // Clear PWM3A on period
    EPwm3Regs.AQCTLB.bit.CAU = AQ_SET;           // Set PWM3A on event A, up
#else

#if 1
    /*
     *
     SR1(EPWM3A): Set after B close before C
     SR2(EPWM3B): Set after A
     */
    //mode 1
    EPwm3Regs.AQCTLA.bit.ZRO =  AQ_SET;
    EPwm3Regs.AQCTLA2.bit.T1U = AQ_CLEAR;   // PCM
    EPwm3Regs.AQCTLA.bit.CAU =  AQ_CLEAR;  //   voltage mode
    EPwm3Regs.AQCTLA.bit.PRD =  AQ_CLEAR;

    EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
    EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR;
    EPwm3Regs.AQCTLB.bit.CBD = AQ_SET;    // for duty limit or voltage mode
    EPwm3Regs.AQCTLB2.bit.T1D = AQ_SET;


    EPwm3Regs.AQCTL.bit.SHDWAQAMODE = 1;
    EPwm3Regs.AQCTL.bit.SHDWAQBMODE = 1;
    EPwm3Regs.GLDCTL.bit.GLDPRD = 1;
    EPwm3Regs.GLDCTL.bit.GLD = 1;

    // mode 2 testing
    //EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
    //EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR;
    //EPwm3Regs.AQCTLB.bit.CAU  = AQ_CLEAR;
    //EPwm3Regs.AQCTLB2.bit.T1U = AQ_CLEAR;       // for peak current mode different with EPWM2
#else
    // mode2
    EPwm3Regs.AQCTLA.bit.ZRO =  AQ_SET;
    EPwm3Regs.AQCTLA2.bit.T1D = AQ_SET;         // peak current mode  different with EPWM2
    EPwm3Regs.AQCTLA.bit.CBD  = AQ_SET;         // for voltage mode
    EPwm3Regs.AQCTLA.bit.PRD = AQ_CLEAR;

    EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
    EPwm3Regs.AQCTLB.bit.PRD = AQ_CLEAR;
    EPwm3Regs.AQCTLB.bit.CAU  = AQ_CLEAR;
    EPwm3Regs.AQCTLB2.bit.T1U = AQ_CLEAR;       // for peak current mode different with EPWM2
#endif

#endif

    // dead time

    EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm3Regs.DBCTL.bit.IN_MODE  = DBA_RED_DBB_FED;
    EPwm3Regs.DBCTL.bit.POLSEL   = DB_ACTV_HIC;
    EPwm3Regs.DBCTL.bit.OUTSWAP  = 0x03;            // A: B-path  B: A-path


    EPwm3Regs.DBFED.all = SR_DT;
    EPwm3Regs.DBRED.all= SR_DT;                                                 // count


    EALLOW;

    EPwm3Regs.AQTSRCSEL.bit.T1SEL          = 3;// DCBEVT2 to be T1

#if 1
    //Configure EPWM2B to output low on  TRIP
    EPwm3Regs.TZDCSEL.bit.DCBEVT2          = TZ_DCBH_HI;
    EPwm3Regs.DCTRIPSEL.bit.DCBHCOMPSEL    = 0xF; //DCBHTRIPSEL
    EPwm3Regs.DCBHTRIPSEL.bit.TRIPINPUT4   = 1;
    //Configure DCB as CBC
    EPwm3Regs.DCBCTL.bit.EVT2SRCSEL        = DC_EVT1;
    EPwm3Regs.DCBCTL.bit.EVT2FRCSYNCSEL    = DC_EVT_ASYNC;

    EPwm3Regs.TZCLR.bit.CBC                = 1;
#endif

    EDIS;




    // Interrupt where we will change the Compare Values
    EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;    // Select INT on Zero event
    EPwm3Regs.ETSEL.bit.INTEN = 0;               // Enable INT
    EPwm3Regs.ETPS.bit.INTPRD = ET_3RD;          // Generate INT on 3rd event

#endif

}
//*******************************************************************************
// function : InitEPwm4Example
// Description:  Configure the  EPWM4 as timing control of ramp and blanking window
//*******************************************************************************
void InitEPwm4Example(int PRD)
{

    // Setup TBCLK
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up/down and down
    EPwm4Regs.TBPRD = PRD-1;           // Set timer period
    EPwm4Regs.TBCTL.bit.PHSEN = 1;        // Disable phase loading
    EPwm4Regs.TBPHS.bit.TBPHS = 4;            // Phase is 0
    EPwm4Regs.TBCTR = 0x0000;                      // Clear counter
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm4Regs.TBCTL.bit.SYNCOSEL = 3;
    EPwm4Regs.TBCTL2.bit.SYNCOSELX = 1;

    // Setup shadow register load on ZERO
    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    EPwm4Regs.HRPCTL.bit.PWMSYNCSELX = 4;  // CMPC  up
    EPwm4Regs.CMPC = PRD -10;

    EPwm4Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
    EPwm4Regs.AQCTLA.bit.PRD = AQ_CLEAR;
    EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR ;
    EPwm4Regs.AQCTLA2.bit.T1U = AQ_SET;
    EPwm4Regs.CMPA.bit.CMPA  = 210;

    EALLOW;
    EPwm4Regs.AQTSRCSEL.bit.T1SEL          = 3;// DCBEVT2 to be T1
    //Configure EPWM2B to output low on  TRIP
    //EPwm4Regs.TZCTL.bit.TZA               = TZ_FORCE_LO;
    //EPwm4Regs.TZCTL.bit.TZB               = TZ_FORCE_LO;
    //Configure DCB to be TRIP4
    EPwm4Regs.TZDCSEL.bit.DCBEVT2          = TZ_DCBH_HI;
    EPwm4Regs.DCTRIPSEL.bit.DCBHCOMPSEL    = 0xF; //DCBHTRIPSEL
    EPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT4   = 1;
    //Configure DCB as CBC
    EPwm4Regs.TZSEL.bit.DCBEVT2           = 0;
    //Configure DCB path to be unfiltered & async
    EPwm4Regs.DCBCTL.bit.EVT2SRCSEL        = DC_EVT2;
    EPwm4Regs.DCBCTL.bit.EVT2FRCSYNCSEL    = DC_EVT_ASYNC;

    EPwm4Regs.TZCLR.bit.CBC                = 1;

    EPwm4Regs.DCFCTL.bit.PULSESEL = 0x10;
    EPwm4Regs.DCFCTL.bit.SRCSEL   = 3;
    EPwm4Regs.DCFWINDOW  = 0x60;
    EPwm4Regs.DCFCTL.bit.BLANKE   = 1;
    EDIS;

}

I capture the waveform from F280049 control card. If you want to look it , i would prepare how i setup it.

Brian

0 Subrahmanya over 7 years ago in reply to Brian Chang90901

TI__Mastermind 24095 points

Brian,

Looking through your code and the wave forms above,
From the wave forms - it seemed like you want have active high complimentary outputs.
Is this correct?
So, in the PWM configuration I see -
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
Did you want to have both outputs A/B generated out of A in Active high complimentary mode?
if so, you need to make it
EPwm2Regs.DBCTL.bit.IN_MODE = DBB_ALL;

0 Brian Chang90901 over 7 years ago in reply to Subrahmanya

TI__Intellectual 2540 points

No not complimentary more.

Both A/ B need rising edge dead time. The timing diagram was as bellowing

We fund this issue first time when we change the CTRIPH to latch signal from the signal after digital filter.

The B channel will be wrong behavior. it look like PWMB change the output after the CTRIPH was reset.

Today , i try to change EPWM3A as same configuration as EPWM2B.

At the same testing condition , it look like workable and did not have such fault.

However , the solution would lead us to occupy more ePWM module.

Brian Chang

0 Subrahmanya over 7 years ago in reply to Brian Chang90901

TI__Mastermind 24095 points

Brian,

Your diagram seems to indicate EPWM1/2 outputs as active high complimentary.
PWM1/2B is complimentary and inverted version of PWM1/2A.
So, i still think that you should be using EPwm2Regs.DBCTL.bit.IN_MODE = DBB_ALL;
Maybe i'm misunderstanding the requirement here.
Are you saying that your application works if you use EPWM3A instead of EPWM2B - though they are with same configuration?

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TMS320F280049: Unexpect PWM output by using CMPSS to provide the T1/T2 event