TMS320F28034: NMI Watchdog missing detection

Hisao,

Two counters are used to monitor the presence of the OSCCLK signal - the first counter is incremented by the OSCCLK signal itself, and when the PLL is not turned off, the second counter is incremented by the VCOCLK coming out of the PLL block. These counters are configured such that when the 7-bit OSCCLK counter overflows, it clears the 13-bit VCOCLK counter. In normal operating mode, as long as OSCCLK is present, the VCOCLK counter will never overflow.

If the OSCCLK input signal is missing, then the PLL will output a default limp mode frequency and the VCOCLK counter (13-bits = 8192) will continue to increment. Since the OSCCLK signal is missing, the OSCCLK counter will not increment and, therefore, the VCOCLK counter is not periodically cleared. Eventually, the VCOCLK counter overflows and, if required, the device switches the CLKIN input to the CPU to the limp mode output frequency of the PLL.

Therefore, the actual time will depend on the user’s configuration for the PLL and the value the VCOCLK was at before the missing clock happened. Please see the "TMS320F2803x Piccolo System Control and Interrupts Reference Guide" - SPRUGL8, page 43 for additional information:

www.ti.com/lit/sprugl8

I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

- Ken