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CCS/TMS320F28377D: Asynchronous EMIF(32-bit mode), Address pin is shifted.

user3662711
Prodigy 80 points

Part Number: TMS320F28377D

Tool/software: Code Composer Studio

Hi,

I have a trouble using Asynchronous EMIF(TMS320F28377D), so I would like to ask you a question.

Detailed questions are as follows.

1. Test procedure

- In order to user asynchronous EMIF 32-bit mode, source code was configured in the below.

- CS3, Address A0, A1 and Data D0, D1 pins were monitored by using oscilloscope.

2. Test results

- CS3 pin worked well.

- Data D0 and D1 worked well.

- Address A0 and A1 were shifted.(Although I programmed to output high signal from A1, the high signal was output from A0).

- In technical reference manual 2612 page, If I set 'Emif1Regs.ASYNC_CS#_CR.bit.ASIZE = 2(32bit mode)', A0 is least significant bit.

3. Questions

- I can't understand why A0, A1 were shifted.

- To use A0 pin properly, which additional register should I set except 'Emif1Regs.ASYNC_CS#_CR.bit.ASIZE = 2' ?

Regards,

Uiseok

SOUCE CODE

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

#include "F28x_Project.h"

#include "F2837xD_device.h"

#include "F2837xD_Examples.h"

 

extern void setup_emif1_pinmux_async_16bit(Uint16);

void EMIF_init(void);

 

#define BASEADDR 0x300000

#define DAC_A *((unsigned long*)(BASEADDR | 0x0))       //-- DAC A

#define DAC_B *((unsigned long*)(BASEADDR | 0x1))       //-- DAC B

#define DAC_C *((unsigned long*)(BASEADDR | 0x2))       //-- DAC C

#define DAC_D *((unsigned long*)(BASEADDR | 0x3))       //-- DAC D

 

Uint16 DAC_DATA = 0, DAC_DATA_b =0, DAC_DATA_c =0, DAC_DATA_d = 0;

 

void main(void)

{

    InitSysCtrl();

 

    EMIF_init();

 

    DINT;

 

    InitPieCtrl();

 

    EALLOW;

    IER = 0x0000;

    IFR = 0x0000;

    EDIS;

 

    InitPieVectTable();

 

    while (1)

    {

        DAC_A = DAC_DATA;

        DAC_B = DAC_DATA_b;

       DAC_C = DAC_DATA_c;

        DAC_D = DAC_DATA_d;

     }

}

 

void EMIF_init(void)

{

EALLOW;

ClkCfgRegs.PERCLKDIVSEL.bit.EMIF1CLKDIV = 0x0;

EDIS;

 

EALLOW;

Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE71;

if(Emif1ConfigRegs.EMIF1MSEL.all != 0x1)

{

ErrCount++;

}

Emif1ConfigRegs.EMIF1ACCPROT0.all = 0x0;

if(Emif1ConfigRegs.EMIF1ACCPROT0.all != 0x0)

{

ErrCount++;

}

Emif1ConfigRegs.EMIF1COMMIT.all = 0x1;

if(Emif1ConfigRegs.EMIF1COMMIT.all != 0x1)

{

ErrCount++;

}

Emif1ConfigRegs.EMIF1LOCK.all = 0x1;

if(Emif1ConfigRegs.EMIF1LOCK.all != 1)

{

ErrCount++;

}

EDIS;

 

setup_emif1_pinmux_async_16bit(0);

 

EALLOW;

Emif1Regs.ASYNC_CS3_CR.bit.ASIZE = 2;                    // 1:0 Asynchronous Memory Size.

Emif1Regs.ASYNC_CS3_CR.bit.TA = 3;                        // 3:2 Turn Around cycles.

Emif1Regs.ASYNC_CS3_CR.bit.R_HOLD = 7;                 // 6:4 Read Strobe Hold cycles.

Emif1Regs.ASYNC_CS3_CR.bit.R_STROBE = 15;             // 12:7 Read Strobe Duration cycles.

Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = 1;                 // 16:13 Read Strobe Setup cycles.

Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = 3;                 // 19:17 Write Strobe Hold cycles.

Emif1Regs.ASYNC_CS3_CR.bit.W_STROBE = 12;             // 25:20 Write Strobe Duration cycles.

Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP = 1;                // 29:26 Write Strobe Setup cycles.

Emif1Regs.ASYNC_CS3_CR.bit.EW = 0;                        // 30 Extend Wait mode.

Emif1Regs.ASYNC_CS3_CR.bit.SS = 0;                         // 31 Select Strobe mode.

EDIS;

}

 

 

void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel)

{

    Uint16 i;

 

    for (i=28; i<=52; i++)

    {

        if ((i != 42) && (i != 43))

        {

            GPIO_SetupPinMux(i,cpu_sel,2);

        }

    }

    for (i=63; i<=87; i++)

    {

        if (i != 84)

        {

            GPIO_SetupPinMux(i,cpu_sel,2);

        }

    }

 

    GPIO_SetupPinMux(88,cpu_sel,3);

    GPIO_SetupPinMux(89,cpu_sel,3);

    GPIO_SetupPinMux(90,cpu_sel,3);

    GPIO_SetupPinMux(91,cpu_sel,3);

    GPIO_SetupPinMux(92,cpu_sel,3);

    GPIO_SetupPinMux(93,cpu_sel,3);

    GPIO_SetupPinMux(94,cpu_sel,2);

 

    //

    //setup async mode and enable pull-ups for Data pins

    //

    for (i=69; i<=85; i++)

    {

        if (i != 84)

        {

            GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP

        }

    }

}

  • 0
    TI__Guru** 117431 points

    Hi,

    From following statement, it's not clear what exactly the issue is -

     - Address A0 and A1 were shifted.(Although I programmed to output high signal from A1, the high signal was output from A0).

    What do you mean by "high signal on A1"? Can you please explain it with some example?

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 80 points

    Hi, Vivek Singh
    Thank you for your prompt reply.

    Here is an example.
    I programmed A0 - low, A1 - high, A2 - high.
    However, when I monitored A0, A1 and A2 pin by oscilloscope, address shift is appeared like below.


    Source code           TMS320F28377D              oscilloscope
    A0 : Low       ------->                              -------->   A0 : High
    A1 : High      ------->                              -------->   A1 : High
    A2 : High.     ------->                              -------->   A2 : Low

    Regards,
    Uiseok

  • 0 in reply to user3662711
    TI__Guru** 117431 points
    What do you mean by program address lines? What is the address you are writing/reading from in code? Please note that address lines are 32bit alligned address so if you are writing at address 0x2 from C28x side then you'll see ox1 on address lines (32bit alligned address) and byte enables will be used to choose to correct byte.

    Regards,
    Vivek Singh
  • 0 in reply to user3662711
    TI__Guru 62975 points

    Uiseok,

    Try changing your pointer defines to use either unsigned int addresses:

    #define BASEADDR 0x300000
#define DAC_A *((unsigned int*)(BASEADDR | 0x0))       //-- DAC A
#define DAC_B *((unsigned int*)(BASEADDR | 0x1))       //-- DAC B
#define DAC_C *((unsigned int*)(BASEADDR | 0x2))       //-- DAC C
#define DAC_D *((unsigned int*)(BASEADDR | 0x3))       //-- DAC D

     or change your address offsets to be 32-bit aligned even numbers only:

    #define BASEADDR 0x300000
#define DAC_A *((unsigned long*)(BASEADDR | 0x0))       //-- DAC A
#define DAC_B *((unsigned long*)(BASEADDR | 0x2))       //-- DAC B
#define DAC_C *((unsigned long*)(BASEADDR | 0x4))       //-- DAC C
#define DAC_D *((unsigned long*)(BASEADDR | 0x6))       //-- DAC D

    -Tommy

  • 0 in reply to tlee
    Prodigy 80 points
    Hi, tommy.

    Thank you for your advice.

    Your First suggestion showed the same result as my code.
    However, the second suggestion showed exactly right operation.

    I will find out the relation between address offset and base address.
    Thanks a lot.

    Uiseok.
  • 0 in reply to Vivek Singh
    Prodigy 80 points
    Thanks.
    I will refer to it.

    Uiseok.