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TMS320F28032: How to calculate High Resolution Bits?

user4997907
Intellectual 270 points

Part Number: TMS320F28032

Hello,

I've read through the data sheet and there wasn't really a clean cut formula to determine the high-resolution PWM bits in order to determine the resolution. Is there any one that knows of a formula for it?

Thanks!

  • 0
    TI__Mastermind 42195 points

    user4997907,

    There is no formula for the step size of the HRPWM. In our documentation we refer to this as a MEP step size. The datasheet has a typical and a max value published in section 6.9.10.1 "HRPWM Electrical Data/Timing".

    Note 1:The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher temperature and lower voltage and decrease with lower temperature and higher voltage.

    Note 2:Each MEP step is not exactly the same size some will be larger than others.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 270 points
    How are the resolution bits calculated in the documentation for HRPWM then? Let's assume we have a fixed MEP SIZE of 180ps, Operating at 60Mhz with a desired PWM frequency of 300kHz, using the UP DOWN Symmetrical Scheme?
  • 0 in reply to user4997907
    Expert 2530 points

    Hi,

    do you mean how to determine bit count from non power of two maximum count N? It's log(N) / log(2). Full steps at 60MHz clock and 300kHz PWM is 200? 180ps microsteps in 1/60MHz - about 92. So N = 200 * 92, resolution bits ~14.1. In symmetric mode since up and down count is the same, resolution is 2 times lower, resolution bits is one less, ~13.1 bits. 

    Edward

  • 0 in reply to user4997907
    TI__Mastermind 42195 points

    user4997907 said:
    How are the resolution bits calculated in the documentation for HRPWM then?

    When the F2803x device was first produced it underwent validation. During this validation high-accuracy equipment was used to observe the PWM's output as the HRPWM was configured and used across a large number of operating conditions. Several engineers then carefully reviewed the data taken and placed those numbers into the datasheet.

    user4997907 said:
    Let's assume we have a fixed MEP SIZE of 180ps, Operating at 60Mhz with a desired PWM frequency of 300kHz, using the UP DOWN Symmetrical Scheme?

    Sorry, I do not understand what this question is asking. Operating at 60 Mhz will not affect your PWM's resolution. You can use the HRPWM to generate a PWM at a frequency of 300 kHz signal. Up-Down count mode should be OK.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 270 points

    Ah, thank you for the background on the calculations then!

    According to sprug8e, page 17/44 it indicates that the operating frequency does play a role in the resolution

    -Christian

  • 0 in reply to user4997907
    TI__Mastermind 42195 points

    Christian,

    The MEP step size isn't changing the period of the PWM is changing, thus the number of steps that fit into that period changes. See the example calculation I did below, all of the step sizes are roughly 180, whoever made the table did some rounding.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 270 points
    Cody,

    The MEP changes during run time, which is why the SFO function is required. Is that no so? But i'm not fixed on the MEP. If we consider a PWM clock of 60Mhz, if I wanted a PWM frequency of 300kHz and the prescalers divs were both 1. Wouldn't it be (60e6/300e3) = 200 for TBPRD?
    Now if we had a 40MHz clock it would be (40e6/300e3) = 133.333333333 for TBPRD. I'm confused how the Master Clock doesn't affect resolution?
    If we have a higher frequency clock we can finely subdivide the output of the PWMs. Isn't this so???

    -Christian
  • 0 in reply to user4997907
    TI__Mastermind 42195 points

    Christian,

    user4997907 said:
    The MEP changes during run time, which is why the SFO function is required. Is that no so?

    The MEP does change during runtime, and yes the SFO will help compensate for it. It however does not allow you to adjust it to 10 MEP steps per SYSCLK period.

    user4997907 said:
    I'm confused how the Master Clock doesn't affect resolution?

    When talking about the ePWM; you are correct, exactly as you have pointed out, SYSCLK(Master Clock) does affect the resolution. When talking about HRPWM; the period of SYSCLK does not change the length of a MEP step size, the two are completely unrelated.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 270 points
    Yes I was aware that the MEP isnt affected by the Frequency. The only reason I've mentioned it is because I wanted to know how to calculate the High Resolution in terms of Bits in order to gauge how much wiggle room I have.

    Thank you very much Cody!

    Edward, thank you for the formula!

    Our TBPRD is calculated as follows: (SYSCLKOUT/(2*PWM_FREQ))
    -> This is a product of using the Up Down Counter Mode.

    Bits = log2((SYSCLKOUT/PWM_FREQ) * MEP_STEPS)
    MEP_STEPS = T_SYSCLKOUT/MEP_SECONDS
    -> MEP_SECONDS = [150, 310]ps -> CHECK DATA SHEET
    -> We can run calculations at both best and worst case

    ------------------------------------------------------------------
    @ 60Mhz - @ 180ps MEP_SECOND
    (1/60e6)/180e-12 = 92.5925925926 -> 93

    w/ Up Down Count @ 300kHz
    Bits = 13.1830150009
    ------------------------------------------------------------------
    @ 60Mhz - @ 310ps MEP_SECOND
    (1/60e6)/310e-12 = 53.7634408602 -> 54

    w/ Up Down Count @ 300kHz
    Bits = 12.3987436919
    ------------------------------------------------------------------