Compiler/TMS320F28377S: CCS/TMS320F28377S

//#############################################################################
//
// FILE:   upp_sdr_tx_cpu01.c
//
// TITLE:  upp transmit example for F2837xS
//
//! \addtogroup cpu01_example_list
//! <h1> UPP Single Data Rate Transmit (upp_sdr_tx) </h1>
//!
//! This example sets up the F2837xS board's UPP with the single-data-rate(SDR)
//! interface as a transmitter.
//!
//! \b Important: In order to run this example, two F2837xS boards are required.
//! All the UPP pins from one board to the other must be connected with common
//! ground. One board must be loaded with this example code and the other board
//! must be loaded with the "upp_sdr_rx" example.
//!
//! \b Instructions:
//! # Load the "upp_sdr_tx" on board 1
//! # Load the "upp_sdr_rx" on board 2
//! # Run the "upp_sdr_rx" code on board 2 (Needs to be run before the tx code)
//! # Run the "upp_sdr_tx" code on board 1
//!
//! \b Watch \b Variables: \n
//! - \b TEST_STATUS - Equivalent to \b TEST_PASS if test finished correctly,
//!                    else the value is set to \b TEST_FAIL
//! - \b ErrCount - Error counter
//!
//
//
//      |-----------|               |-----------|
//      |           |=====D0-D7=====|           |
//      |  Device   |-----CLK-------|   Device  |
//      |  Board-1  |               |   Board-2 |
//      |    TX     |-----ENABLE----|     RX    |
//      |           |-----START-----|           |
//      |-----------|               |-----------|
//
//#############################################################################
// $TI Release: F2837xS Support Library v3.01.00.00 $
// $Release Date: Mon May 22 15:44:59 CDT 2017 $
// $Copyright:
// Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################

// Included Files
//
#include "F28x_Project.h"
#include "F2837xS_Upp_defines.h"

// Defines
//
#define TEST_PASS		0xABCDABCD
#define TEST_FAIL		0xDEADDEAD
#define LINE_CNT		1//4//
#define WORD_CNT		6
#define BYTE_CNT		WORD_CNT*2//64//
#define WIN_CNT			1//8//
#define WIN_BYTE_CNT	WORD_CNT*2*LINE_CNT//256//
#define WIN_WORD_CNT	WORD_CNT*LINE_CNT//128//
#define LINEOFFSET		0
#define TAKE_NNN		0x1//0xAAAB // ������� �������� ���� �� TMS � FPGA
#define BUTTON			59 // GPIO59 J2 Pin14
// Globals
//
volatile long int ErrCount;
volatile long int TEST_STATUS = TEST_FAIL;
volatile long int eow_int_cnt = 0;
volatile long int eol_int_cnt = 0;
volatile long int RdValue = 0;
volatile long int WrValue = 0;
volatile int InitTxMsgRam = 0;

// Function Prototypes
//
extern void InitUpp1Gpio(void);
extern void SoftResetUpp(void);
interrupt void local_UPPA_ISR(void);
int i,iii=0,jj=0,kk=0,ll=0,mm=0,nn=0,p=0,r=0,s=0,btn=0,mem=0,data=1,tmp=0;
// Main
//
void main(void)
{
   TEST_STATUS = TEST_FAIL;
   ErrCount = 0x0;
   GPIO_SetupPinMux(BUTTON, GPIO_MUX_CPU1, 0);//
   GPIO_SetupPinOptions(BUTTON, GPIO_INPUT, GPIO_PUSHPULL | GPIO_INVERT | GPIO_ASYNC);//,  |GPIO_PULLUP

// Initialize System Control
   InitSysCtrl();

   DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flaLS
// are cleared.
// This function is found in the F2837xS_PieCtrl.c file.
//
   InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:

   EALLOW;
   IER = 0x0000;
   IFR = 0x0000;
   EDIS;

// Initialize the PIE vector table with pointers to the shell Interrupt
// LService Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xS_DefaultIsr.c.
// This function is found in F2837xS_PieVect.c.

   InitPieVectTable();

   EALLOW;
   PieVectTable.UPPA_INT = &local_UPPA_ISR;

// Enable the Interrupt No 8.
   IER = M_INT8 ;

// Enable Interrupt for UPPA Interrupt.
   PieCtrlRegs.PIEIER8.bit.INTx15=1;

// Enable PIE & CPU level Interrupts.
   EnableInterrupts();

// Issue Soft Reset (internal) to uPP.
   SoftResetUpp();

// Configure the GPIO muxing for uPP pins.
// mux = 15, �.�. GPAGMUX1 = 3 � GPAMUX1 = 2. disable pull-up (GPAPUD = 1),
   // Async input (no Sync or Qualification) GPAQSEL1 = 3
   InitUpp1Gpio();

// Initialize the TX MSG RAM. #define uPP_TX_MSGRAM_SIZE 512 ��� ���������� ������ 512�16
   for (i = 0; i < uPP_TX_MSGRAM_SIZE ; i+=1)
	   *(Uint32 *)(uPP_TX_MSGRAM_ADDR + i) = 0;

   *(Uint32 *)(uPP_TX_MSGRAM_ADDR) = data;//TAKE_NNN;
// Configure uPP for TX
   UppRegs.IFCFG.bit.CLKDIVA = 0xF;//0x4; // 0x4: Div8. Clock divider for transmit mode: TX_IOCLK = CHIP_CLK / 2(N+1)
   UppRegs.IFCFG.bit.CLKINVA = 1;		 // 1: Clock is inverted
   UppRegs.CHCTL.bit.MODE = uPP_TX_MODE; // Setup for TX. 01: Pure output transmit mode.
   UppRegs.CHCTL.bit.DRA = uPP_SDR;      // SDR mode 0: Single Data Rate (SDR)
   UppRegs.IFIVAL.all = 0x0000;          //Idle Value. When in transmit mode, this field holds the value that will
   	   	   	   	   	   	   	   	   	   	 //  be driven  out when the channel is idle
   GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;  // 1: Disable pull-up on GPIO10 (uPP_WAIT)
   UppRegs.IFCFG.bit.WAITA = 1;		// 1: Enable (Tx: honor wait)
   UppRegs.IFCFG.bit.WAITPOLA = 1;  // 1: Active Low. 0: Active High.

	for(;;)
	{
		*(Uint32 *)(uPP_TX_MSGRAM_ADDR) = data;//TAKE_NNN;
		// Enable EOL/EOW interrupt
	   UppRegs.INTENSET.bit.EOLI = 1; // 1: Interrupt enable for end-of-line condition.
	   UppRegs.INTENSET.bit.EOWI = 1; // 1: Interrupt enable for end-of-line condition.
	   UppRegs.GINTEN.bit.GINTEN = 1; // 1= uPP generates interrupt to if interrupt flag gets set
	   UppRegs.PERCTL.bit.PEREN = 1; //1: Enable/Resume the uPP module

	// Setup DMA channel
	   UppRegs.CHIDESC0 = uPP_TX_MSGRAM_ADDR;// Starting address of the DMA Channel I transfer.
	   UppRegs.CHIDESC1.bit.LCNT = LINE_CNT; // Number of lines in a window for DMA Channel I transfer
	   UppRegs.CHIDESC1.bit.BCNT = BYTE_CNT; // Number of bytes in a line for DMA Channel I transfer
	   UppRegs.CHIDESC2.all = LINEOFFSET;//BYTE_CNT;//		 // Line Offset Address. Offset from the current line starting address to the next line
											 // starting address for DMA Channel I transfers

	   PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;// = 0�80
	   while (eow_int_cnt < WIN_CNT); // WIN_CNT = 8 // eow_int_cnt ������������ � ����������� ����������

	// Disable the uPP to stop transmission after expected window count is done.
	   UppRegs.PERCTL.bit.PEREN = 0; // 0: Disable/Suspend the uPP module
//			asm("          ESTOP0");
	   eow_int_cnt = 0;
	   eol_int_cnt = 0;
	// Determine example test status
	   if (ErrCount == 0x0)
		  TEST_STATUS = TEST_PASS;
	}
}

// local_UPPA_ISR - UPPA Interrupt Service Routine (ISR)
interrupt void local_UPPA_ISR(void)
{
   // To receive more interrupts from this PIE group, acknowledge this interrupt
   int i;
//   jj++;
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;// = 0�80

   if (UppRegs.GINTFLG.all != 0x0) // 1: Interrupt has been generated.
   {
//       kk++;
	   if(UppRegs.ENINTST.bit.EOWI == 0x1) //Check for EOW Interrupt flag
         {									 // 1: End Of Window event happened
//           ll++;
		   eow_int_cnt++;
            if (eow_int_cnt < (WIN_CNT - 1)) // WIN_CNT = 8
            {
             InitTxMsgRam = 1;
            }

            //Enable EOL interrupt ��������� ���� ���������� �� Window, ������ ���� � ���������� EOL
            UppRegs.INTENSET.bit.EOLI = 1; // Interrupt enable for end-of-line condition

            //Clear the Status for EOW Interrupt Writing 1 will clear the interrupt status
            UppRegs.ENINTST.all = uPP_INT_EOWI; // =8; Interrupt enable status for end-of-Window condition.
            if (UppRegs.ENINTST.bit.EOWI != 0)	// ���� �� ��������� ����?
            {
                ErrCount++;
                asm ("      ESTOP0");
                for(;;);//�������� �����, ���� ������
            }
         }
         if(UppRegs.ENINTST.bit.EOLI == 0x1) // Check for EOL Interrupt Flag
         {// ����� EOWI �� ����, � EOLI ���������
//            nn++;
        	 eol_int_cnt++;

            // Disable EOL Interrupt. Writing 1 will clear the interrupt status
            UppRegs.ENINTST.all = uPP_INT_EOLI;// = 0x10; Interrupt enable status for end-of-line condition.
            if (UppRegs.ENINTST.bit.EOLI != 0)// ���� ���� �� ���������
            {
                ErrCount++;
                asm ("      ESTOP0");
                for(;;);//�������� �����, ���� ������
            }
            UppRegs.INTENCLR.all = uPP_INT_EOLI;// Interrupt clear for end-of-line condition.
            									// Writing 1 will disable the interrupt
            if (UppRegs.INTENSET.bit.EOLI != 0)
            {
                ErrCount++;
                asm ("      ESTOP0");
                for(;;);//�������� �����, ���� ������
            }

            // Initialize the Channel Descriptor for Next window transfer.
								if (eow_int_cnt < (WIN_CNT -1))//���� �� ��� ���������
								{
//									mm++;
									if (eow_int_cnt%2)//������� �� �������
									{
										if(InitTxMsgRam == 1)
										{
											 for (i = 0; i < WIN_WORD_CNT ; i+=2)
											 {
												WrValue = WrValue + 0x12345678;
												*(Uint32 *)(uPP_TX_MSGRAM_ADDR + i) = WrValue;
											 }
											 InitTxMsgRam = 0;
										}
										 UppRegs.CHIDESC0 = uPP_TX_MSGRAM_ADDR;//����� � �������� ������ ������������. ���������� �����������������
										 UppRegs.CHIDESC1.bit.LCNT = LINE_CNT;
										 UppRegs.CHIDESC1.bit.BCNT = BYTE_CNT;
										 UppRegs.CHIDESC2.all = LINEOFFSET;//BYTE_CNT;//
									}
									else
									{
										if(InitTxMsgRam == 1)
										{
											for (i = 0; i < WIN_WORD_CNT ; i+=2)
											{
												WrValue = WrValue + 0x12345678;
												*(Uint32 *)((uPP_TX_MSGRAM_ADDR +
															 WIN_WORD_CNT) + i) = WrValue;
											}
											InitTxMsgRam = 0;
										}
										UppRegs.CHIDESC0 = uPP_TX_MSGRAM_ADDR + (LINE_CNT *
																				 BYTE_CNT);
										UppRegs.CHIDESC1.bit.LCNT = LINE_CNT;
										UppRegs.CHIDESC1.bit.BCNT = BYTE_CNT;
										UppRegs.CHIDESC2.all = LINEOFFSET;//BYTE_CNT;//
									}
								}
         }

      // Clear Global Interrupt.
      RdValue = UppRegs.ENINTST.all;
      UppRegs.GINTCLR.bit.GINTCLR = 1;
      if (UppRegs.GINTFLG.all != 0x0)
      {
          ErrCount++;
          asm ("      ESTOP0");
          for(;;);//�������� �����, ���� ������
      }
   }
}

//
// End of file
//