TMS320F28379D: Requirement of TBCTL[PHSEN] and HRPCTL[TBPSHRLOADE] configuration for ePWM High-Resolution period configuration in up-down count mode

Hi Hrishi,

In the example hrpwm_deadband_sfo_v8, the high-resolution phase is required along with high resolution hence it makes sense to enable the PHSEN and TBPHSHRLOADE in the ISR when the values of HR registers are updated.

By my concern is why do we need to enable it if we are working only with high-resolution period TBPRD and TBPRDHR and if we are do not need any phase shift? In the same path there is one more example hrpwm_prdupdown_sfo_cpu01 as I mentioned before. In the example PHSEN is not set anywhere and TBHSRLOADE is set to 1 in the initialization function as shown below.

void HRPWM_Config(period)
{
Uint16 j;

//
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edge
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the EPWM
EDIS;

for(j=1; j<PWM_CH; j++)
{
(*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
(*ePWM[j]).TBPRD = period; // PWM frequency = 1/(2*TBPRD)
(*ePWM[j]).CMPA.bit.CMPA = period / 2; // set duty 50% initially
(*ePWM[j]).CMPA.bit.CMPAHR = (1 << 8); // initialize HRPWM extension
(*ePWM[j]).CMPB.bit.CMPB = period / 2; // set duty 50% initially
(*ePWM[j]).CMPB.all |= 1;
(*ePWM[j]).TBPHS.all = 0;
(*ePWM[j]).TBCTR = 0;

(*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down
// count mode
(*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
(*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
(*ePWM[j]).TBCTL.bit.FREE_SOFT = 11;

(*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // LOAD CMPA on CTR = 0
(*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
(*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
(*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

(*ePWM[j]).AQCTLA.bit.CAU = AQ_SET; // PWM toggle high/low
(*ePWM[j]).AQCTLA.bit.CAD = AQ_CLEAR;
(*ePWM[j]).AQCTLB.bit.CBU = AQ_SET; // PWM toggle high/low
(*ePWM[j]).AQCTLB.bit.CBD = AQ_CLEAR;

EALLOW;
(*ePWM[j]).HRCNFG.all = 0x0;
(*ePWM[j]).HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on
// both edges.
(*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR
// HR control.
(*ePWM[j]).HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0
// and CTR = TBPRD
(*ePWM[j]).HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on
// both edges
(*ePWM[j]).HRCNFG.bit.CTLMODEB = HR_CMP; // CMPBHR and TBPRDHR
// HR control
(*ePWM[j]).HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD; // load on CTR = 0
// and CTR = TBPRD
(*ePWM[j]).HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for
// HR period

(*ePWM[j]).HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
// (required for updwn
// count HR control)
(*ePWM[j]).HRPCTL.bit.HRPE = 1; // Turn on high-resolution
// period control.

CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within
// the EPWM
(*ePWM[j]).TBCTL.bit.SWFSYNC = 1; // Synchronize high
// resolution phase to
// start HR period
EDIS;
}
}

When i run the example, the high resolution period works properly even without enabling the PHSEN.

If I try to enable the PHSEN in the above example, the waveform will be totally different than expected. This is because, the INPUT5SELECT of InputXbarRegs is confgured for GPIO0 by default, and ePWM produces PWM output on GPIO0. So whenever there is a pulse in GPIO0 due to the PWM waveform, the phase syncs with the up-down counter as GPIO0 acts as sync input signal. This causes the up-down counter to restart TBPHS value is 0, resulting in a different waveform.

So my question is why do we need to enable PHSEN for high resolution period TBPRDHR modification when we do not need a phase shift?

Thanks,
Aditya