TMS320F28377D: Interfacing External ADC MAX1312ECM with TMS320F28377D

Hi Ramesh,

It looks like communication to this external ADC is via an ad-hoc parallel interface, so you'll have to develop your own communication drivers by reading and understanding the external ADC datasheet. The two sources you linked will give you a general idea of how this would work.

Any particular reason to use an external 12-bit ADC vs the 4 x 12-bit ADCs already on the device?

Hi devin,

Thanks for your reply.

We go for external ADCs due to many reasons.

(i) expecting higher resolution 

(ii) need many ADC channels(32 Nos)

(iii) to overcome noise related issues & easily adapting to our existing design

My main doubt is about selection of external ADC SOC.

Pls refer the following table.Actually,we need 24 ePWMs with 176 pin package for our application.

So,there are some restrictions in using GPIO pin resources. 

Routing GPIO8 (which is originally assigned for PWM5A) to start of conversion pin of external ADC (MAX1312) will lead to running out of PWM channels.

Pls refer the following figure for external ADC timing characteristics.

Without violating the above timing parameters,

Can i take any GPIO pin & simply route to start of conversion pin of external ADC (MAX1312)?

or Can i use cross bar(X bar) structure as shown below to initiate external ADC SOC?

In the following figure,what does ADCSOCEXT meant for? 

Pls solve my doubts regarding the above queries.

The schematic for interfacing external ADC with TMS320F28337D is shown below.

Kindly check each MCU GPIO pins that are interfaced with external ADC & confirm whether the following scheme is OK.

regards,

Ramesh P

Hi Ramesh,

Are you going to use 4 of these external ADCs to get to 32 channels?

As far as the ADC resolution, a rough comparison is:

	F28377D (12-bit)	MAX1312
Resolution	12-bits	12-bits
MSPS	4 x 3.5MSPS	4? x 1.1MSPS
ENOB	11.1	11.4
ENOB @ fin = ?	100kHz	500kHz
Ch	20	32
Range	0 to ~3.0V	+/- 10V
INL	+/-2 LSBs	+/-1 LSBs
Gain Error	+/-5 LSBs	+/-16 LSBs
Offset Error	+/-4 LSBs	+/-16 LSBs

So resolution is not the issue. 

As far as ENOB, the internal ADC is slightly lower, but considering you can get roughly +0.5 bits of ENOB by oversampling 2x and the internal ADC is >3x faster, this also shouldn't be a problem.

If you have high BW input signals >> 100kHz that might be a good reason to use the specific external ADC. 

The external ADC also has the potential for a wide input range, but adding a bunch of external ADCs is probably more complicated than adding signal conditioning circuits to get the inputs into range.

Accuracy is much better on the internal ADC.  

If you an place the external ADCs far enough away from the noisy power stage of the system you certainly might be able to get some isolation from noise.  

Overall I think it'd probably be easier to use two F28377S or just add an external mux to the internal ADCs.

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As far as selecting an external ADC, we can't help you much with non-TI parts, but if you post in the precision ADC e2e forum with your external ADC requirements they'll be happy to help you select from the many excellent TI ADCs.

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Any GPIO should be fine for the various external ADC signals, but you can make life much easier on yourself if you select a contiguous and byte-aligned group of GPIO for D0 to D11.  e.g. GPIO32 - GPIO43.  This will ease packing/unpacking data to write to or read from the parallel interface.

ADCEXTSOC is not what you want for interfacing to an external ADC; this is for an external trigger coming in to trigger the on-chip ADCs.

ADCSOCAO or ADCSOCBO are the outputs you'd want.  These come from the PWMs to trigger an external ADC.  This output signal is pulse-stretched per the timings in figure 5-53 that you quoted above. 

Hi Devin,

Thanks for your detailed reply.

Now.I got some points.As u suggested,I will post my requirement in e2e forum soon.

Meanwhile,pls make me clear the following doubt.

For data lines D0-D11,can we use any GPIO pins other than dedicated for External memory interface 1 data line as shown below ?

Is the following sequence OK for contiguous parallel datalines ?

GPIO69     - D0
GPIO70     - D1
GPIO71     - D2
GPIO72     - D3
GPIO73     - D4
GPIO74     - D5
GPIO75     - D6
GPIO76     - D7
GPIO77     - D8
GPIO78     - D9
GPIO79     - D10
GPIO80     - D11

Thanks & regards,

Ramesh P

Hi Ramesh,

Any GPIO is fine. GPIO muxed with the EMIF are fine too as long as you aren't using the EMIF (or at least not using those specific EMIF pins).

The GPIO are organized into banks:

GPA = GPIO0 to GPIO31
GPB = GPIO32 to GPIO63
GPC = GPIO64 to GPIO96
etc.

Things should be relatively easy as long as the GPIO are contiguous and in the same bank, so GPIO69 to GPIO80 is a good choice.

The easiest would be the lowest 12 GPIO in a bank since you wouldn't have to rotate the value before writing or after reading, but this isn't really that big of a deal.