Part Number: TMS320F28031
Hi,
I am trying to get the ECAN0INTA interrupt enabled for reception and then service it with the ECAN0INTA_ISR function which is a part of the DSP2803x_DefaultIsr.c file. Here are the steps that I have followed:
Step 1: Configuring the interrupt: (Please note that the CAN communication is perfectly working and currently we use it by polling the CANRMP register, but we need that ISR to work additionally.)
// EXAMPLE TEMPLATE AND STEPS TO CONFIGURE INTERRUPTS ON CAN
//##########################################################################################################################
// MBOX15 is an RX mailbox that receives distributed control output. Because of the time critical nature the reception
// from this mailbox is controlled using interrupts
// First all CAN interrupts other than mailbox TX-RX interrupts will be disabled. The following registers contains
// enable/disable control for all events other than RX-TX (eg.. Bus-Off, Timeout, Abort Acknowledge etc..)
ECanaRegs.CANGIM.all = 0;
// Next Select the interrupt line for the particular mailbox. We have 2 choices: ECAN1INT or ECAN0int line.
// 0: ECAN0INT level selected
// 1: ECAN1INT level selected
// We will go with ECAN0INT
ECanaShadow.CANMIL.all = ECanaRegs.CANMIL.all;
ECanaShadow.CANMIL.bit.MIL15 = ECAN0INT_LEVEL_SELECT; // Select ECAN0INT level for generating MBOX15 interrupts
// {Others by default are also configured for ECAN0INT level but we don't care)
ECanaRegs.CANMIL.all = ECanaShadow.CANMIL.all;
// Enable MBOX15 Mailbox interrupt
ECanaShadow.CANMIM.all = ECanaRegs.CANMIL.all;
ECanaShadow.CANMIM.bit.MIM15 = ENABLE_INT;
ECanaRegs.CANMIM.all = ECanaShadow.CANMIM.all;
// Enable ECAN0INT at the peripheral level
ECanaShadow.CANGIM.all = ECanaRegs.CANMIL.all;
// ECanaShadow.CANGIM.bit.I0EN = ENABLE_INT;
ECanaShadow.CANGIM.all = 0xFFFFFFFF;
ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;
//##########################################################################################################################
EDIS;
}
As you can see, I am simply setting the interrupt for the Receive Mailbox 15 at Level 0.
Step 2: Configuring the ISR handling:
EALLOW;
/* Use Default Isr vectors */
PieVectTable.ADCINT1 = ADCINT1_ISR;
PieVectTable.ECAP1_INT = ECAP1_INT_ISR;
PieVectTable.SCIRXINTA = SCIRXINTA_ISR;
PieVectTable.ECAN0INTA = ECAN0INTA_ISR;
PieVectTable.ECAN1INTA = ECAN1INTA_ISR;
/* Enable Interrupt at PIE level */
PieCtrlRegs.PIEIER1.bit.INTx1 = ENABLE_INT_PIE_LEVEL; // ADCINT1 interrupts
PieCtrlRegs.PIEIER4.bit.INTx1 = ENABLE_INT_PIE_LEVEL; // ECAP1_INT interrupt
PieCtrlRegs.PIEIER9.bit.INTx1 = ENABLE_INT_PIE_LEVEL; //Scia Rx interrupts
ACKNOWLEDGE_GROUP_INTERRUPT(PIEACK_GROUP9);
EDIS;
/* Step 9: Enable Interrupt at CPU Level */
IER |= (M_INT9 | M_INT4 | M_INT1); // Enable Group9, Group4 and Group1 Interrupts at the CPU level (M_INT9 is nothing but 0x0100)
I am doing this for enabling the group 9 (Note that the ADC_ISR, SCI_ISR, ECAN_ISR work perfectly. In fact, SCI_ISR is in the same group as ECAN that is group 9).
I can't get the ECAN0INT_ISR to work by doing the above. Is there something that I am missing out?
