This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F8335 SPUFB0D PLL Ambiguity

Hi

I'm using TMS320F8335 microcontoller. On my board I 'm using a 25 Mhz external oscillator clock. Now I must set PLL register to set the cpu CLKIN.

On  page 43 I find this :

"PLL enabled mode
When the PLL control register is non-zero (PLLCR = n, where n ≠ 0x0000), the PLL is enabled. In this
mode, OSCCLK*n, OSCCLK*n/2, or OSCCLK*n/4 is connected to CLKIN of the CPU. If OSCCLK is
detected as missing, the missing clock detect status bit will be set and the device will generate a
missing clock reset. The device will now run at one-half of the PLL limp mode frequency."

So if PLLCR[DIV]= 6 and PLLSTS[DIVSEL]=3   CLKIN=(25 *6)/1=150 Mhz

But on page 41 I have found table 20 where is written :

PLL Enabled         Achieved by writing a non-zero value n into the PLLCR register. Upon                             0, 1 OSCCLK*n/4
                                writing to the PLLCR, the device will switch to PLL Bypass mode until                              2 OSCCLK*n/2
                                the PLL locks.

So it seems I can't set the THE PLLSTS[DIV]=3 and PLLCR[DIV]= 6 to obtain a CLKIN =150Mhz

Can somebody explain me which is the wrong configuration and which the correct?

Can I set PLLSTS[DIVSEL]=3  and PLLCR[DIV]= 6?

Thanks

Angelo

  • Angelo -

    The correct answer is that, on TMS320F2833x/F2823x devices, PLLSTS[DIVSEL] = 3 (/1 mode) should NOT be used.  The reason for this is in the data-sheet 4th note under Table 3-16. PLL Settings:

    (4) A divider at the output of the PLL is necessary to ensure correct duty cycle of the clock fed to the core. For this reason, a DIVSEL value
    of 3 is not allowed when the PLL is active.

     Basically, since the 2833x/2823x devices run at such a high frequency, if there is no PLL divider (via the DIVSEL bits) of at least /2, the system clock duty cycle will not be maintained properly - which will cause timing issues in the core and for certain timing-sensitive peripherals.

    Note: The data sheet is always the "golden" resource when compared to the user guides.  I agree that the statement in SPRUFB0 is ambiguous and will mark that as something to be updated.