Hi
I'm using TMS320F8335 microcontoller. On my board I 'm using a 25 Mhz external oscillator clock. Now I must set PLL register to set the cpu CLKIN.
On page 43 I find this :
"PLL enabled mode
When the PLL control register is non-zero (PLLCR = n, where n ≠ 0x0000), the PLL is enabled. In this
mode, OSCCLK*n, OSCCLK*n/2, or OSCCLK*n/4 is connected to CLKIN of the CPU. If OSCCLK is
detected as missing, the missing clock detect status bit will be set and the device will generate a
missing clock reset. The device will now run at one-half of the PLL limp mode frequency."
So if PLLCR[DIV]= 6 and PLLSTS[DIVSEL]=3 CLKIN=(25 *6)/1=150 Mhz
But on page 41 I have found table 20 where is written :
PLL Enabled Achieved by writing a non-zero value n into the PLLCR register. Upon 0, 1 OSCCLK*n/4
writing to the PLLCR, the device will switch to PLL Bypass mode until 2 OSCCLK*n/2
the PLL locks.
So it seems I can't set the THE PLLSTS[DIV]=3 and PLLCR[DIV]= 6 to obtain a CLKIN =150Mhz
Can somebody explain me which is the wrong configuration and which the correct?
Can I set PLLSTS[DIVSEL]=3 and PLLCR[DIV]= 6?
Thanks
Angelo