Tool/software: Code Composer Studio
Hello,
I need to produce a specific startup sequence on a PWM, so I am trying to create a simple assembly file that makes the waveform by forcing action qualifiers, then I free the lines and fire the PWM in counter UP mode.
I located the routine in RAM memory for execution. I placed the function on a separate C file, and disabled optimizations. The issue I have is that 97% pecent of time it executes with a fixed number of cycles, but remaining three percent of time there are 9 extra cycles that are added and affects my timing. Could you kindly provide some light where this sporadic 9 cycles may be coming from?
I am measuring by debugging session, I add a break point on the LCR instruction that calls the function, and run up to another breakpoint on the instruction just below the LCR. This routine is called with interrupts disabled, for that I am using _disable_interrupts(); / _enable_interrupts() directives:
void func Enable_PWM(){
_disable_interrupts();
/* configure registers on PWM */
/* ... */
/* perform start sequence */
Pwm_StartSequence();
/* PWM is fired and running here, I do some other activities and I am done */
_enable_interrupts();
}
Thanks in advance and best regards,
Alberto Peyro
Here is the assembly code being called from C file above. Before this function, basically the PWM is set for forcing action qualifier, CNTR is loaded with start count of 40 out of a maximum of PRD= 285 (count up mode). Pwm_LLCMgr.h contains just some additional #define labels... I am using compiler TI v16.9.4.LTS
.def _Pwm_StartSequence
.cdecls C,LIST,"Pwm_LLCMgr.h"
TBCTL_reg .set 0x00 ;register offset
TBCTR_reg .set 0x04 ;register offset
AQSFRC_reg .set 0x47 ;register offset
AQCSFRC_reg .set 0x49 ;register offset
DBCTL_reg .set 0x0C ;register offset
DBCTL2_reg .set 0x0D ;register offset
DBRED_reg .set 0x51 ;register offset
DBFED_reg .set 0x53 ;register offset
Pulse_High_20percent1 .set 57-2-1
Pulse_High_20percent2 .set 57-2-1
Pulse_Low_30percent1 .set 86-2-1
Pulse_Low_30percent2 .set 4
OutA_Low_OutB_Low .set 5
OutA_High_OutB_Low .set 6
OutA_Low_OutB_High .set 9
DisableSoftwareForcing .set 0
EnableCountUP .set 0xFFFC
LoadOnCNT_PRD .set 0x0040
TwoCycleDelay .set 2
.sect ".TI.ramfunc"
_Pwm_StartSequence:
;; set pointers to registers
MOV ACC,@AR4 ;;pointer to TBCTL
NOP
NOP
ADD ACC,#DBCTL_reg
MOVL XAR5,ACC ;;pointer to DBCTL
ADD ACC,#(AQSFRC_reg-DBCTL_reg)
MOVL XAR6,ACC ;;pointer to AQSFRC
ADD ACC,#(AQCSFRC_reg-AQSFRC_reg)
MOVL XAR7,ACC ;;pointer to AQCSFRC
MOV ACC,@AR4 ;;pointer to TBCTL
RPT #TwoCycleDelay || NOP
ADD ACC,#DBRED_reg
MOVL XAR1,ACC ;;pointer to DBRED
RPT #TwoCycleDelay || NOP
MOV ACC,@AR4 ;;pointer to TBCTL
RPT #TwoCycleDelay || NOP
ADD ACC,#DBFED_reg
MOVL XAR2,ACC ;;pointer to DBFED
RPT #TwoCycleDelay || NOP
;;set LOW
MOV *+XAR7[0], #OutA_Low_OutB_Low
RPT #TwoCycleDelay || NOP
;;20% pulse in A
MOV *+XAR7[0], #OutA_High_OutB_Low
RPT #Pulse_High_20percent1 || NOP
MOV *+XAR7[0], #OutA_Low_OutB_Low
;;Wait 30% low
RPT #Pulse_Low_30percent1 || NOP
;;20% pulse in B
MOV *+XAR7[0], #OutA_Low_OutB_High
RPT #Pulse_High_20percent2 || NOP
MOV *+XAR7[0], #OutA_Low_OutB_Low
EALLOW
;;Set DBCTL
MOV *+XAR5[0], #DEADBAND_REG_PRE_DISABLE
RPT #TwoCycleDelay || NOP
MOV *+XAR7[0], #9
RPT #TwoCycleDelay || NOP
MOV *+XAR5[0], #DEADBAND_REG_ENABLE
RPT #TwoCycleDelay || NOP
;;free software forcing on period
MOV *+XAR6[0], #LoadOnCNT_PRD
RPT #TwoCycleDelay || NOP
;;disable software forcing
MOV *+XAR7[0], #DisableSoftwareForcing
RPT #TwoCycleDelay || NOP
;;fire counter / assume counter is freeze
AND *+XAR4[0], #EnableCountUP
RPT #TwoCycleDelay || NOP
EDIS
LRETR
