• State Resolved
  • Locked Locked
  • Replies 15 replies
  • Answers 2 answers
  • Subscribers 82 subscribers
  • Views 1426 views
  • Users 0 members are here
Support feedback
Options
Options

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TMS320F28379D: SDFM data sync-read probem with ePWM reset signal

Yonglu Hu
Prodigy 140 points
Part Number: TMS320F28379D
Other Parts Discussed in Thread: CONTROLSUITE

Tool/software: Code Composer Studio

Hi，everybody, I have several questions about SDFM and ePWM.

1. We use ePWM1-3 as the motor PWM output and use ePWM12 to sync reset SDFM module, but we want SDFM module to grab data at each time ePWM1-3 start trigger. How can I sync ePWM1 and ePWM12?

2. In the TI demo (D:\ti\controlSUITE\development_kits\TMDSIDDK_v2.0\IDDK_PM_Servo_F2837x_v2_00_00_00), I find follow settings: 

"EPwm11Regs.CMPC = EPwm11Regs.TBPRD - SDFM_TICKS*(OSR_RATE+1)*3/2;
EPwm11Regs.CMPA.bit.CMPA = (SDFM_TICKS*(OSR_RATE+1)*3/2) + 500; // 500 is arbitrary
EPwm11Regs.CMPD = 0;"

As we want to grab SDFM data when ePWM1-3 start trigger, but SDFM module need a latency(our latency is 38.9us), I set ePWM11: CMPC/D = CMPA = 0; and in the 100us-MotorControlISR module, I add a "while", waiting(about 38.9us) for SDFM.SDIFLG.AF1-3 to be all 1, then clear the flag. But I failed, only to find the program stop running after a few second. Why?

3. I don't quite understand the setting of CMPC and CMPA values, according to spec of 28379: Latency of Sinc filter = Order of Sinc filter * OSR /Modulator data rate, then fomula in CMPC and CMPA should be (3*(OSR_RATE+1)/SDFM_TICKS/2)*100, but why TI demo set values as above?

Thanks forward.

  • 0
    Prodigy 140 points
    Q1.I've known the method to solve question 1, just use following settings:
    SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN = 0;
    EPwm10Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    Q4. But I've got another question just now, since latency of sinc filter is about 3 sampling cycles(as for us, data rate is 78.125k, that is 12.8 us/sample), but the spec tells us that only "first two samples of sinc3 filter are incorrect", so I set CMPC two-sample-time(25.6us) ealier than CMPA, thus, I think I can get the SDFM data just when the motor ISR trigger, but still need one sampling cycle(12.8us), so I wait in the "while" until SDFM.SDIFLG.AF1-3 to be all 1, I thought it needs about 12.8us, but my test shows it won't cost that much time, and just like sync with the motorISR. Why is this?
  • 0 in reply to Yonglu Hu
    TI__Mastermind 27240 points
    Sampling should be done corresponding to the carrier peak point. With Sync filter working with N samples, the native latency is N/2. That is why, we start the new conversion at N/2 samples ahead of carrier peak point and wait for another N/2 samples after the peak point to read the data. An arbitrary count of 500 was just additional cycles to ensure the SDFM registers are all fully updated by the time the ISR reads the data. Ofcourse, this 500 count is very heavily over done, and can be reduced by more than 20 times.
    As for your experience on waiting on the SDFM flags, we need to figure out what is going on.
  • 0 in reply to Ramesh Ramamoorthy
    TI__Guru 55700 points
    Yonglu,

    Are all the 3 filter channels (Filter 1 / 2 / 3) configured the same way? If not, data rate of Sinc filters would be different.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    Prodigy 140 points

    Thanks for your reply.

    Yes, 3 filter channels are configured the same way. Comparator: sinc3 filter, osr_32. Data-filter: sinc3, osr_128, data_16bit, shift_6_bit. Enable MFE, enable external_reset,  enable MFIE interrupt, enable AE interrupt.

  • 0 in reply to Yonglu Hu
    TI__Guru 55700 points
    Yonglu,

    I need clarification on data acknowledge flag question. Are you concerned that the flags aren't setting as expected?

    Please clarify.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    Prodigy 140 points
    In the motorISR, I add the "while" as bellow:
    while(!((*SDFM[gPeripheralNumber]).SDIFLG.bit.AF1
    && (*SDFM[gPeripheralNumber]).SDIFLG.bit.AF2
    && (*SDFM[gPeripheralNumber]).SDIFLG.bit.AF3));
    I grab the data after this and then, I clear the flag as bellow:
    (*SDFM[gPeripheralNumber]).SDIFLGCLR.bit.AF1 = (*SDFM[gPeripheralNumber]).SDIFLG.bit.AF1;
    (*SDFM[gPeripheralNumber]).SDIFLGCLR.bit.AF2 = (*SDFM[gPeripheralNumber]).SDIFLG.bit.AF2;
    (*SDFM[gPeripheralNumber]).SDIFLGCLR.bit.AF3 = (*SDFM[gPeripheralNumber]).SDIFLG.bit.AF3;
    Is there any problem?
  • 0 in reply to Yonglu Hu
    TI__Guru 55700 points
    You are using while loop to wait for all the 3 flags (AFx) toset. This is fine.
    It is not necessary to clear the flags individually. You can clear all the 3 flag with just only instruction. But, its upto you.

    Regards,
    Manoj
  • 0 in reply to Ramesh Ramamoorthy
    Prodigy 140 points

    Hi，Ramesh

    I'm still confused about the value of latency. According to the fomula TI demo shows, the result of "SDFM_TICKS*(OSR_RATE+1)*3" is 1920, I think its meaning is that the time value is 1920/100=19.2us, is this the same with "N" you mean? But according to spec of 28379d,  "Order of Sinc filter * (OSR+1) /SDFM_TICKS" should be 76.8us, it's 4 times of 19.2us. 
  • 0 in reply to Yonglu Hu
    TI__Guru 55700 points
    Yonglu Hu,

    Value of SDFM_TICKS depends upon SD-modulator frequency. If SD-modulator is operated at 20 MHz, then SDFM_TICKS is 5 (representing 5ns (1/20MHz)). When modulator is operated at 10MHz, then SDFM_TICKS is 10 (representing 10ns (1/10MHz).

    In the example mentioned in TRM, it assumes that SD-modulator frequency is 10MHz and DOSR = 256. If your earlier post, you mentioned your DOSR = 128.

    'N' is the number of samples you want to read from SDFM filter in one PWM cycle. In the IDDK_PM_Servo_F2837x_v2_00_00_00 example, number of samples read / PWM cycle is 1. So, N = 1.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    Prodigy 140 points

    Hi， Manoj,

    Thanks so much. I took the frequency with 5MHz for mistake. According to 20MHz frenquency, "Data rate of Sinc Filter" equals to 156.25K samples/sec(6.4us), and "Sinc filter latency" equals to 19.2us(=3*6.4us). As the spec tells, the first two samples of the Sinc3 filter are incorrect, so I can understand time value of 19.2us as treble of sample time, to get correct data. But if I want to sync with the point PWM1-3 trigger(ET_CTRU_PRD), shouldn't CMPC vale to be "EPwm11Regs.TBPRD-(SDFM_TICKS*(OSR_RATE+1)*3*2/3)", that is EPwm11Regs.TBPRD--(6.4*2 = 12.8)?

  • 0 in reply to Yonglu Hu
    TI__Mastermind 27240 points

    The total number of samples needed with sinc3 filter for your case is 384 (OSR=128, OSR_RATE = 127). (Total time is 19.2us, midpoint is at 9.6us). To sync the midpoint with EPWM PRD event, SDFM should start at 9.6us ahead of the PRD event.

    9.6us ==> (SDFM_TICKS*(OSR_RATE+1)*3/2

    So, CMPC = PRD - 9.6us 

    ==> EPwm11Regs.TBPRD-(SDFM_TICKS*(OSR_RATE+1)*3/2)

    Hope it helps.

  • 0 in reply to Ramesh Ramamoorthy
    Prodigy 140 points

    Hi, Ramesh,

    Sorry, I've just seen your reply and I'm still not that clear. 

    Yes, I agree the total time is 19.2us, but "start the new conversion at N/2 samples ahead of carrier peak point" makes me confused. I think 19.2us = 3*6.4us, 6.4us, which means SDFM sample period(Am I right?). According to the spec, first 2 samples of sinc3 is incorrect, so if I want to get SDFM data sync with EPWM PRD event, why it is not "start the new conversion at N*2/3 samples ahead of carrier peak point and wait for N*1/3 samples after the peak point to read the data"? 

    Look forward to your kind reply.

  • 0 in reply to Yonglu Hu
    Prodigy 140 points
    Add:
    - Cause the Data rate of Sinc Filter = 20MHz/128=1156.25K samples/sec, then one sample period should be 128/20MHz=6.4us. Am I right?
    - The last sentence above, I mean start conversion at 2 samples(2*6.4us=12.8us) ahead, and then wait for 1 sample(6.4us) after the peak point to read data. Why TI demo use 1.5 sample ahead and 1.5 sample after conversion?
  • 0 in reply to Yonglu Hu
    TI__Mastermind 27240 points
    Since the first two samples are not useable in a sinc3 filter, we ignore them. The third is useable. But, this output uses all the 192 samples up till that time, including the 128 of them that were used in the previously ignored outputs. 1.5 sample is because the sinc3 being an FIR, its output will have a delay of N/2 samples. Therefore, the output of sinc3 filter will correspond to 192/2 = 96 samples ahead or in other words, 96 samples since starting FIR.
  • 0 in reply to Ramesh Ramamoorthy
    Prodigy 140 points

    Hi, Ramesh

    Thanks so much for your patient explanation. I get it.