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TMS320F28335: tms320f28335 not getting stable ADC output.

Part Number: TMS320F28335


Hi, I'm working on f28335. I want to display ADC data of f28335 on 16x2 LCD display. I read datasheet ADC and configure register of ADC for ADCINA0 in continuous scanning mode. My board is customized and thus parameters used for ADC are kept as

Oscillator freq= 20MHz

Systemclk= 100MHz

ADC in voltage= 0-3 Volt (which I am varying by wiper of 100K potentiometer) 

fortunately i am getting results for the same but the result in watch window varies in between 50 to 60 samples. Please help me with this problem. Thank you so much.

  • Hi,

    Anshuman Tech said:
    fortunately i am getting results for the same but the result in watch window varies in between 50 to 60 samples.

    You mean 50-60 digital counts, right? I hope you've a suitable RC filter at your ADC input.

    Regards,

    Gautam

  • As Gautam mentioned you will need to take into account the internal RC sampling network of the F28335 ADC as well as the sampling speed of the ADC when trying to get stable ADC results.  

    If you have fed the potentiometer input directly into the ADC, without any buffering or external capacitance, it will likely give readings within the range you have seen.

    A rule of thumb with an ADC input, is that we need to make the input at least 1-bit more accurate than the ADC that is sampling to not introduce addition error into the conversion.  In this case we need to make sure that the settled voltage is 13-bit accurate.

    I'd recommend this app note to explain this a bit more:

    http://www.ti.com/lit/an/spraas1c/spraas1c.pdf  Look at section 3.4.2.1

    Best regards,

    Matthew

  • Thankyou Gautam and Mathew for your suggestions. I've gone through Hardware  Design Guidelines and made changes as per requirement.

    I made filter of 30pF cap and 100ohm resistor as mentioned in manual in 3.4.2.1 on page number 13.

    But still I'm getting the same variation with same speed. 

  • Anshuman,
    Let's increase the sample and hold window(ACQPS) of the ADC to its max value, and see if it helps. This will increase the amount of sampling time/time for the internal S/H cap to settle to the voltage you have on the pin.

    I believe the 30pf/100ohm combo is assuming an ideal input/buffered input. If there is ~100kohm load on the ADC pin it will have significant kickback when the sample and hold circuit closes. Without a buffer we will need a bigger cap(which will lead to delays in the response time but we can address that later).

    Best,
    Matthew