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TMS320F28379D: EPWM - Clarification on the Digital Compare submodule synchronization events

Part Number: TMS320F28379D

Hello,

I am trying to use the ePWM module in a very particular way but I am not 100% that my design will in fact work.

Basically, we use two comparators to generate TRIP events based on a high and low threshold of a same analog input.

When the analog input goes above the high treshold, the comparator output is latched after a filtering period.

When the analog input goes below the low threshold, we are trying to reset the latched output on the first comparator.
For that, we thought we could be forwarding the TRIP event of the low threshold comparator (we inverted the output in the cmpss module), towards the digital subcompare module.
Then we were thinking we would redirect the digital subcompare module even to the EPWMSYNCO output of the EPWM module thanks to the Time Base submodule as this sync signal can be used to reset the latched comparator output.

So in our configuration, the inverted output of the low threshold comparator will be remain active as long as the analog input stays below the treshold.
However what I am unsure of is, will it generate successive reset pulses on the DCxEVT.sync output of the submodule which we configured as being triggered when DCxH is high and DCxL don't care ? Or will it generate only a pulse on rising edge of DCxH ?

Note that when thinking about it, as our low threshold is below the high one successive reset would not be an issue but I want to clarify the behavior.

Clément

  • Hi,

    It seems your configuration could work. Few notes below.
    What exactly is setting and clearing the PWM output? Is it the comparator events or PWM time base events?

    "will it generate successive reset pulses on the DCxEVT.sync output of the submodule which we configured as being triggered when DCxH is high and DCxL don't care ? Or will it generate only a pulse on rising edge of DCxH ?"

    if you are using "DCEVTFILT" as the source with the blanking window, you should see an event every time after the blanking window, even if the input is static.
    Refer to Figure 14-51. DCAEVT2 Event Triggering, Figure 14-54. Event Filtering
    If you are using the raw event or no blanking - you may see event generation only during the transition.

    I'm not sure if your question/concerns are fully addressed. What exactly is your observation?

  • Hi,

    Subrahmanya Bharathi said:

    It seems your configuration could work. Few notes below.
    What exactly is setting and clearing the PWM output? Is it the comparator events or PWM time base events?

    As a matter of fact, we don't plan to use the PWM outputs.

    We are just using the PWM peripheral as a mean of reseting the CMPSS latched output of our comparator.

    I know that's a bit odd but it was the only way we found to make a sort of automated SW free mechanism.

    Subrahmanya Bharathi said:

    "will it generate successive reset pulses on the DCxEVT.sync output of the submodule which we configured as being triggered when DCxH is high and DCxL don't care ? Or will it generate only a pulse on rising edge of DCxH ?"

    if you are using "DCEVTFILT" as the source with the blanking window, you should see an event every time after the blanking window, even if the input is static.
    Refer to Figure 14-51. DCAEVT2 Event Triggering, Figure 14-54. Event Filtering
    If you are using the raw event or no blanking - you may see event generation only during the transition.

    I'm not sure if your question/concerns are fully addressed. What exactly is your observation?

    I guess it is, we have not tried that yet.

    Clément

  • Hi,

    This is very interesting use of CMPSS/EPWM function. You can try the above and share your observations.