Dhaivat,
You could use a 150 MHz, but I am curious to know the reason, considering 150 MHz oscillators are considerably more expensive than, say, a 30 MHz quartz crystal. Is there a reason you wouldn't want to take advantage of the on-chip PLL that can multiply a 30 MHz input clock to 150 MHz?

Hi Hareesh,

I did not see much cost saving. Also by using 150MHz wanted to improve reliability and remove delays associated with PLL circuitry. I am a bit nervous about using the XCLKOUT signal of this DSP which I intend to use as a clock for a FPGA in my design. Knowing the fact that it reaches the nominal freq in stages.

Per Table 5-4 of the datasheet, you should be able to employ XCLKIN = 150 MHz.

Hi Hareesh,

I am slightly confused with datasheet.

My aim is to have 150MHz clock to CPU and produce XCLKOUT to be 75MHz along with PLL enabled. I was also intending to use 150MHz external oscillator clock for this purpose.

Please see my question again.

If we want to use PLL, Table5-9 in the datasheet shows the cycle time for (XCLKIN) 33.3ns (min) & 200ns (max).

Does this mean that the frequency of external oscillator must be between 5MHz to 30MHz?

OR 

Can I still use 150MHz external oscillator and still have PLL enabled to produce 150MHz SYSCLKOUT and later divide by to to get XCLKOUT = 75MHz.

Best regards,