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CCS/TMS320F28335: ADC conversion channel is not controllable

Z
Intellectual 350 points
Part Number: TMS320F28335

Tool/software: Code Composer Studio

in my program I would like 4 channel conversions. They are ADC channel A3, A1, A2 and A4. I read the conversion results in ADCRESULT0, ADCRESULT1, ADCRESULT2, ADCRESULT3.

The ADC setup is the following:

AdcRegs.ADCTRL3.bit.SMODE_SEL =0x0;
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 0 Non-Cascaded Mode; 1 Cascaded Mode 

AdcRegs.ADCMAXCONV.all = 0x0003; // Setup 3 conv's on SEQ1
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x3; // Setup ADCINA3 as 1st SEQ1 conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA1 as 2nd SEQ1 conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup ADCINA2 as 3nd SEQ1 conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x4; // Setup ADCINA4 as 4nd SEQ1 conv.

The result is that all 16 channels are sampling even though I specify AdcRegs.ADCMAXCONV.all = 0x0003;

What is the cause? How to fix it?

Thank you.

  • 0
    Intellectual 350 points
    If I set to non-cascaded mode, like the following
    AdcRegs.ADCTRL1.bit.SEQ_CASC = 0X0;

    the result is that 8 channels are converted.
    ADCRESULT0, ADCRESULT1, ADCRESULT2, ADCRESULT3, ... to ADCRESULT7 have conversion results.
    ADCRESULT8-15 are all zeros.
  • 0 in reply to Z
    TI__Guru* 80490 points
    Zhiyang,
    When the Sequencer is in non-Continuous Run, it will hold its state at the end of the last conversion. So in this case, after the 1st ADC trigger is processed the Sequencer will be holding at CONV4 when the next trigger comes(either from PWM/external/SW). In your case when the next trigger comes it will process CONV4/5/6/7 and either wrap back to CONV0 if in non-cascaded mode or pend at CONV8.

    There are two options:
    1)If you are processing the ADC ISR at every trigger you can reset the sequencer as part of the ISR.
    2)Fill CONV4/5/6/7 with the same ADC channels such that they will also contain the channel info. This would be useful if you want to have a larger buffer of data before processing the ADC ISR, such that you are not halting the main code to enter into the ISR every 4 conversions. The same applies for cascaded mode; in which you could have 4 sets of your channel data before the ADC would overwrite CONV00.

    Best,
    Matthew