TMS320F28069: Why does 'Non-Overlap Mode' exist? (Question about TMS320F28069 ADC)

Sang-il,
You are correct that for sequential conversions, the use of overlap gives a better sample to result delay that without(a faster overall conversion time). This mode was added to address the 1st sample errata, where from IDLE at max speed the 1st sample converted by the ADC is non-usable.

For systems where there are only a few conversions, or 1 conversion, every ADC trigger this provides a better tradeoff than sampling twice and discarding the 1st sample.

For systems with many back to back conversions the time gained by having overlap active may exceed the time lost in converting and discarding the 1st sample.

So, it really depends on your system if activating non-overlap makes sense. From your initial comments, it may be best to NOT enable this bit in your application; assuming you are OK discarding the 1st sample.

Best,
Matthew