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CCS/TMS320F28379D: epwm interrupt priority

Yonglu Hu
Prodigy 140 points
Part Number: TMS320F28379D


Tool/software: Code Composer Studio

We set epwm as bellow:

EPwm12Regs.TBPRD=10000;

EPwm12Regs.CMPA.bit.CMPA = 1280;

EPwm12Regs.CMPC = 7390;

We use "CMPA event" to trigger an ISR, and use "CMPC event" to reset SDFM,  If the total computation time of ISR is more than (7390-1280=6110), will the CMPC event be blocked? If so, must we control ISR computation time less than 6110 to reset SDFM? 

  • 0
    TI__Guru 60865 points
    Hi Yonglu,

    The compares are a HW mechanism, so the actuation will occur even if you are in an ISR.

    However, if you compute a new compare value and you want it to take effect immediately (you aren't using a shadow load to have it take effect on the next PWM period) then you need to be careful.
    -If your calculation places the new CMPC after the current CMPC, and the current CMPC hasn't yet occurred occured, then everything will be OK.
    -If your calculation places the new CMPC after the current CMPC, but the CMPC has already occured, then the event will occur at the original time, not the new time. This is probably OK, and on the next ePWM cycle it'll occur at the new time.
    -If you calculation places the new CMPC before the current TB count value but the current CMPC hasn't yet occurred, you might miss an event! (the event will only occur exactly when CMPC = TB count). This can be bad depending on the system.