32028335 ADC 'Offset' Problem

Stephan,

Can you comment what the value is in the ADCOFFTRIM register after ADC_CAL routine has ran?  Can you check to make sure there is not any voltage on ADCLO pin?  This should be kept at ground, but if there is a potential here it will show up as offset in the converter.  I would also go ahead and check the values on the ADCREFP and ADCREFM pins to see if there is large delta between this new parts and old parts. 

Best,

Matthew

Hi Matthew,

(Sorry for the delay in response)

The ADCOFFTRIM register reads exactly the following (after the ADC_CAL routine):

ADCOFFTRIM.all = 0x01FB

ADCOFFTRIM.bit.OFFSET_TRIM = 0xFFFB

 There is zero voltage on the ADCLO pin. The ADCREFP is 1.32V, ADCREFM is 0.572V.

I should mention that this only appears on the first sample and hold (A1). It is strange - it doesn't appear to be a straight out offset either. As I increase the value of the input, it appears to track normally once a threshold is reached (i.e. 0.2V or so).

Even stranger, the only difference between 5 working boards and 5 non-working boards is the DSP (from normal to EP). The circuit is the same, but the operation is different.

Stephen,

Are you sampling in sequential or simultaneous sampling mode?  There is errata on goodness of simultaneous sampling: 

Advisory ADC: Simultaneous Sampling Latency
Revision(s) Affected 0, A
Details When the ADC conversions are initiated in simultaneous mode, the first sample pair will
not give correct conversion results.
Workaround(s) 1. If the ADC is used with a sampling window < 160 nS, then the first sample pair must
be discarded and a second sample of the same pair must be taken. For instance, if the
sequencer is set to sample channel A0:B0/A1:B1/A2:B2 in that order, then load the
sequencer with A0:B0/A0:B0/A1:B1/A2:B2 and only use the last three conversions.
2. If the ADC is used with a sampling window greater than 160 ns, there is no issue.

 I initially started with sequential sampling (many months ago), but I think I remember this errata, so I switched to sequential mode. Could it be that the very first sample of the sequential sample is also affected?

My ADC Initialization routine is below:

// Configure ADC
AdcRegs.ADCTRL1.bit.SUSMOD = 0x01; // on Emulation Suspend - Finish CONVERSION (not sequence)
AdcRegs.ADCTRL1.bit.ACQ_PS = 0x00; // Acquisition window size = 1 ADCCLK period
AdcRegs.ADCTRL1.bit.CPS = 1; // ADCCLK = Fclk/1
AdcRegs.ADCTRL1.bit.CONT_RUN = 0; // Stop-Mode Sequencer
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // Sequencer is set as single 16-state
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0; // Do not override sequencer

AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 1; // Cascaded sequence to begin on a CMPB event
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; // Cascaded sequence to begin on a CMPA event
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 0; // Not to begin on a CMPB event
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Generate an interrupt on completion
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0; // on every event

AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x00; // ADCCLK = Fclk
AdcRegs.ADCTRL3.bit.SMODE_SEL = 0; // Sequential Sampling

AdcRegs.ADCMAXCONV.all = 0x000F; // Setup 15 convs

AdcRegs.ADCREFSEL.bit.REF_SEL = 0x00; // Internal Reference

Thanks, can you advise on the HSPCLK divider/XCLKIN value/PLLCR?  I'm basically looking for the ADC clock frequency.  I'm still at a loss to explain the non-EP to EP delta, BTW.

Matt

The CPU is running at 150MHz.

#define PLLCR_VALUE 0x000A // SYSCLKOUT = (OSCLK*10)/2

 SysCtrlRegs.PLLCR.bit.DIV = PLLCR_VALUE;

I also see now that I am running at 12.5MHz (i.e. 12.5MSPS, with CPS = 1 and ADCCLKPS = 0) - where as I should probably be working with 25MHz to get the fastest sampling; I will have to adjust this and test it.

Perhaps increasing the S&H time would help the situation as well.

Some more information regarding the issue:

It seems that the voltage on the previous sample and hold (i.e. A7) seems to have an effect on the 'offset' seen by A1. Could there be some charge coupling when switching the S&H? Do you expect a difference with the EP chips?

Thanks for any help you can provide.

Stephen,

Thanks for the info.  This is interesting, does extending the sample and hold duration remove this delta?  I don't expect this kind of delta(or any delta for that matter), I will need to pass this along to some more folks here for their input.

Best,

Matthew

In fact, yes, it helped the issue substantially.

Changing the ACQ_PS value from 0x00 to 0x01 makes the issue pretty much go away on the A1 channel (increasing to 0x0F will lower the offset of the other channels by just a little bit).

This may be acceptable as a work around, but long term it would be nice to sample at the maximum sample rate without this offset.

Would providing this part of my schematic be of help in diagnosing the issue?

Thanks again,

-- Stephen

Hello

My customer has a very similar problem and from what we can see in the above posts there are 2 routes to remove the simultaneous sampling latency:

1. Take an initial sample and discard this before sampling all other channels.  In our system this can't be done as all 16 ADC channels are being used and so do not have enough registers to hold all samples taken (unless there is a way of sampling without writing to the register?)

2. Lengthen the sample window to be greater than 160ns. Again we are unsure on how to specifically set the sample window and assume it is currently sampling at whatever the default rate is.

If you have any suggestions for the above that would be fantastic!

Regards

Bob Bacon

Hello

My customer has managed to make some progress and tells me

I actually had some success in eliminating the offset!

By setting the ACQ_PS bits of the ADCTRL1 register I was able to extend the sample window  when running in simultaneous sample mode. This has completely removed any ‘offset’ that was present on the A0 ADC.

Would it be worth adding this ‘offset/errata’ issue seen when in simultaneous mode to the TMS320x2833x Analog-to-Digital Converter (ADC) Module Reference Guide (SPRU812A)?

Regards

Bob Bacon