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F28M36P63C2: F28M36P63 decoupling recommendations

Jon Eirik Sternang
Prodigy 460 points

Part Number: F28M36P63C2

According to the datasheet:

VDDIOxxx: "3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-μF capacitor (typical) close to the pin."

However the Controlcard F28M36x_180controlCARD_R1.1 schematics show completely different decoupling structure where groups of 2/3 power pins are tied together and decoupled by a 2.2uF and a bead per group (11 groups).

These does not seem aligned, which decoupling strategy should I use?

25MHz clock in, all pins used, using these peripherals MII/SPI/I2C/UART.

  • 0
    TI__Expert 8105 points
    Jon,

    The datasheet recommendation represents an "ideal" decoupling solution that can be used as a baseline to design practical decoupling solutions for specific "real world" applications. The decoupling strategy used in the Control Card is one such case. Small BGA packages (like the one used by F28M36x) present component placement and signal routing constraints that have to be reconciled with other design parameters - like number of layers used and trace width and cost. For most application it is OK to group pins by tying them to power planes and then connecting decoupling capacitors to same planes. Two things should be kept in mind - the capacitors should be as close to the pins as placement permits, and the total capacitance should be not less than what is specified in the datasheet.