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F2812 ADC Shift

Ricky Zhang
Genius 9520 points

Hi, Champs,

Customer is encountering with ADC issues when using F2812.

Some chips can sample the voltage range from about 20mV to 3V exactly but fail to sample the voltage under 20mV, whose ADC result will be same as the one when ADC input is 20mV.

While some chips can sample the voltage range from about 0V to 2.96V exactly but fail to sample the voltage above 2.96V, whose ADC result will be same as the one when ADC input is 2.96V.

It seems there is vacuum in the boundary (either the 0V or 3V), and we can't calibrate it with software way to compasate the like we do to the gain error and offset error.

So do you have any suggestions on it? Thanks for the information.

 

Best regards,

Ricky Zhang

  • 0
    TI__Guru* 80180 points

    Ricky,

    This is comprehended in the DS specs for this device's ADC as gain error and offset error.  These are +/-200(at FSR) and +/-80LSBs respectively, this overlaps the areas you and customer are seeing that are saturated early.  As you have noted on this device there is no way to recover these regions with SW calibration; this is essentially a keep out zone for the customer and their analog input.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Genius 9520 points

    Matthew,

    Thanks for the confirmation, and I've told customer to keep this zone out. Thank you.

     

    Best regards,

    Ricky Zhang