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TMS320F2808: capture port error

Linda Igboanugo
Intellectual 1820 points

Part Number: TMS320F2808

Hello,

 

we are trying to determine the error that would be seen on the capture port as a function of the internal PLL. (TMS320F2808PZA). The clock source is 20MHz and the internal PPL provides a 100MHz internal clock that is then used for the capture port.

 

The exam question is ultimately, what would be the capture port error using PLL output 100MHz assuming a perfect 20MHz reference.

 

Any help would be much appreciated.

 

Regards

Linda

  • 0
    TI__Mastermind 42195 points
    Linda,
    typically the system clock jitter is less than a system clock, therefore the largest component of jitter is the system clock speed.

    The eCAP may have 1 SYSCLK period of inaccuracy, depending on how the captured edge and the system clock align.

    Regards,
    Cody