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ADC sample rate on the C28335.

William Friesen
Intellectual 990 points

ADC sample rate on the C28335.

Can I set the sample rate on the ADCRESULT0, ADCRESULT1, and ADCRESULT2?  If so how?

Can they all be different?

Will

  • 0
    Genius 5170 points

    I am not sure this forum can cover such a general and vast topic but in short 28335 ADC is flexible and allows you to have separate SOC for each channel and that should allow you to have different sampling rate ... of course you will need to make sure various conversions don't conflict each other ... anyway, your best source of information on this is the ADC manual http://focus.ti.com/lit/ug/spru812a/spru812a.pdf 

  • 0 in reply to Arefeen
    Intellectual 990 points

    Thnx Arefeen,

    I will be reading that document while I await an answer to my next and related question. . .

    Where in the HVMC sensorless FOC 28335 project will I find the sampling rate set?

    Will

  • 0 in reply to William Friesen
    TI__Mastermind 43730 points

    For F28335,

    Look at the Devinit_F2833x.c for the clock division from the main clock, this defined the ADC clock speed wrt to system clock. 

    and if you get to the drivers part of the library look for the f2833xileg_vdc.h, it defines all the sampling SOC's etc... the SOC's are triggered of the PWM's. The PWM's ferequency i already specified in a previous post.

  • 0 in reply to Manish Bhardwaj
    Intellectual 990 points

    I see that in the F2833XILEG_VDC.H file that ADCLKPS is set to Zero.
    I see that in the http://focus.ti.com/lit/ug/sprugi6/sprugi6.pdf Table 1-7 that when ADCLKPS=0 that the ADC samples at 25Mhz (Am I right?)

    But I still confused about some of the timings:

    In HVPM_Sensorless-DevInit_F2833x.c are the following lines:

        PLLset(0xA);    //    10 (or A) means  .. .150MHz

    // HIGH / LOW SPEED CLOCKS prescale register settings
       SysCtrlRegs.HISPCP.all = 0x0002;        // Sysclk / 4 (25 MHz)
       SysCtrlRegs.LOSPCP.all = 0x0002;        // Sysclk / 4 (25 MHz)

    If the clock is at 150MHz, how can Sysclk over 4 be 25MHz?

  • 0 in reply to William Friesen
    TI__Mastermind 43730 points

    Hm.. well i guess the comment there is wrong...

     

    150/4 = 37.5Mhz,

     

    and then we divide the clock inside the ADC as well using the ADCTRL.CPS=1, thus the ADC runs at ~18Mhz... which is within the spec of the device.

     

    The reason why the comment was there was because we have multiple control cards, on a few we can go to 100Mhz and that's what we were running them initially at..

     

    we would fix this comment in the next release, 

    Regards

    Manish Bhardwaj