CCS/LAUNCHXL-F28379D: ADC values not changing.

Hi Ashima,

Probably best to look at the C-source of your code so it will be more readable. Can you also provide the C function being called prior to branching to ASM?

Thanks,
Joseph

//###########################################################################
//
// FILE: adc_soc_epwm_cpu01.c
//
// TITLE: ADC triggering via epwm for F2837xS.
//
//! \addtogroup cpu01_example_list
//! <h1> ADC ePWM Triggering (adc_soc_epwm)</h1>
//!
//! This example sets up the ePWM to periodically trigger the ADC.
//!
//! After the program runs, the memory will contain:\n
//! - \b AdcaResults \b: A sequence of analog-to-digital conversion samples from
//! pin A0. The time between samples is determined based on the period
//! of the ePWM timer.
//
//###########################################################################
// $TI Release: F2837xS Support Library v210 $
// $Release Date: Tue Nov 1 15:35:23 CDT 2016 $
// $Copyright: Copyright (C) 2014-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"



// Function Prototypes
//
void ConfigureADC(void);
void ConfigureEPWM(void);
void SetupADCEpwm(Uint16 channel);


//
// Defines
//
#define FL 65536
#define z11 0.7198
#define z12 0.9732
#define p11 0.1
#define Kp1 -0.001
#define z21 0.9837
#define z22 0.922
#define p21 0.5
#define Kp2 0.012985
#define bum 0.000001

//
// Globals
//
//Uint16 AdcaResults[RESULTS_BUFFER_SIZE];
//Uint16 resultsIndex;
float Vaa[15];
float Iaa[15];
float Err12;
float Err10;
float Err11;
float Err22;
float Err20;
float Err21;
float Dn10;
float Dn11;
float Dn12;
float Dn20=0;
float Dn21;
float Dn22;
//float one;
float Iaf;
float Iaf1;
float Ia;
float Ia1;
float Ia2;
float Ia3;
float Ia4;
float Ias;
float Idc;
float Id;
float Va;
float Va2;
float Va3;
float Va4;
float Vaf;
float Vaf1;
float Vac;
float Iac;
float Va1;
float Vd1;
float Vd2;
float Paf;
float Paf1;
float Pa;
float Pa1;
float Dnf1;
float Dnf2;
float Dn;
float Dn1;
float Vsref=19;
float Vsref1;
float Pp;
float Pdn;
float Vdp;
float Vdn;
float Y;
float Ia1;
float Vas;
Uint16 CMPduty1;
Uint16 CMPduty2;
Uint16 n;


//volatile Uint16 bufferFull;
//
void main(void)

{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xS_SysCtrl.c file.
//
InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xS_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
InitGpio(); // Skipped for this example

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xS_PieCtrl.c file.
//
InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xS_DefaultIsr.c.
// This function is found in F2837xS_PieVect.c.



InitPieVectTable();
EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM2=1;
CpuSysRegs.PCLKCR2.bit.EPWM6=1;
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EDIS;


// Configure the ADC and power it up
//
ConfigureADC();

//
// Configure the ePWM
//
ConfigureEPWM();
// Interrupt where we will change the Compare Values
//
EALLOW;
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = 1; // Generate INT on 3rd event
EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm6Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm6Regs.ETPS.bit.INTPRD = 1; // Generate INT on 3rd event
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = 1; // Generate INT on 3rd event

EDIS;
//
// Setup the ADC for ePWM triggered conversions on channel 0
//
SetupADCEpwm(0);

EALLOW;

//
// Disable internal pull-up for the selected output pins
// for reduced power consumption
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
//
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A)
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B)
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO3 (EPWM2B)
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO3 (EPWM2B)

//
// Configure EPwm-2 pins using GPIO regs
// This specifies which of the possible GPIO pins will be EPWM2 functional pins.
// Comment out other unwanted lines.
//j
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO3 as EPWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO3 as EPWM2B
EDIS;
// Enable global Interrupts and higher priority real-time debug events:
//
IER |= M_INT1; //Enable group 1 interrupts
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//
// enable PIE interrupt
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;

//
// sync ePWM
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;


//start ePWM
//
EPwm2Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm2Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
EPwm6Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm6Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
EPwm3Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm3Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
EDIS;

do
{
EALLOW;
Err12=Err11;
Err11=Err10;
Dn12=Dn11;
Dn11=Dnf1;
Err22=Err21;
Err21=Err20;
Dn22=Dn21;
Dn21=Dnf2;
Paf1=Paf;
Vaf1=Vaf;
Iaf1=Iaf;
Va1=Va;
Va2=Va1;
Va3=Va2;
Va4=Va3;
Ia1=Ia;
Ia2=Ia1;
Ia3=Ia2;
Ia4=Ia3;
Vsref1=Vsref;
for (n=0; n<15; n++)
{
///// Assigning of values
Vd1=AdcbResultRegs.ADCRESULT0;
Va=(3*((2*Vd1/65536)-1)+0.0254)/0.013647;

Idc=AdcaResultRegs.ADCRESULT4;
Ia=15*((2*Idc/65536)-1);

Vd2=AdcbResultRegs.ADCRESULT1;
Va2=250*((2*Vd2/65536)-1);

}
(Vaa[0]+Vaa[1]+Vaa[2]+Vaa[3]+Vaa[4]+Vaa[5]+Vaa[6]+Vaa[7]+Vaa[8]+Vaa[9]+Vaa[10]+Vaa[11]+Vaa[12]+Vaa[13]+Vaa[14]+Vaa[15])/15;

Iaf=(Iaa[0]+Iaa[1]+Iaa[2]+Iaa[3]+Iaa[4]+Iaa[5]+Iaa[6]+Iaa[7]+Iaa[8]+Iaa[9]+Iaa[10]+Iaa[11]+Iaa[12]+Iaa[13]+Iaa[14]+Iaa[15])/15;
Paf=Vaf*Iaf;

for(n=0; n<10000; n++)
{
Err10=19-Vaf;
Dn10=(p11+1)*Dn11-(p11*Dn12)+(Kp1*Err10)-(Kp1*(z11+z12)*Err11)+(Kp1*z11*z12*Err12);
}
// Err20=18-Va2;
// Dn20=(p21+1)*Dn21-(p21*Dn22)+(Kp2*Err20)-(Kp2*(z21+z22)*Err21)+(Kp2*z21*z22*Err22);

//}



if(Dn10>0.8)
{
Dnf1=0.8;
}
else if(Dn10<0.05)
{
Dnf1=0.05;
}
else
{
Dnf1=Dn10;
}
Dnf1=0.4;
// CMPduty1=(20*99*Dnf2);
CMPduty1=(20*99*Dnf2);
EPwm2Regs.CMPA.bit.CMPA = CMPduty1;
CMPduty2=(20*99*Dnf1);
EPwm6Regs.CMPA.bit.CMPA = CMPduty2;
// }
EDIS;
// for (n=1 ; n<100 ; n++)
//{}

} while(1);
}

// ConfigureADC - Write ADC configurations and power up the ADC for both
// ADC A and ADC B
//
void ConfigureADC(void)
{
EALLOW;

//
//write configurations
//
AdcaRegs.ADCCTL2.bit.PRESCALE = 0x0000; //set ADCCLK divider to 200MHz/1
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

//
//Set pulse positions to late
//
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;

//
//power up the ADC
//
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL2.bit.PRESCALE = 0x0000; //set ADCCLK divider to 200MHz/1
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

//
//Set pulse positions to late
//
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;

//
//power up the ADC
//
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;

//
//delay for 1ms to allow ADC time to power up
//
DELAY_US(1000);

EDIS;
}

//
// ConfigureEPWM - Configure EPWM SOC and compare values
//
void ConfigureEPWM(void)
{
EALLOW;
// EPWM2A TRIGGERING FOR PWM
// Assumes ePWM clock is already enabled
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = 4; // Select SOC when CMPA equal to TBPRD
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm2Regs.TBPRD = 20*99; // Set period to 65536 counts
EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = 0;
// Set actions
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A,

// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = 01; // Generate INT on every event // up count

// EPWM6A TRIGGERING FOR PWM
// Assumes ePWM clock is already enabled
EPwm6Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm6Regs.ETSEL.bit.SOCASEL = 4; // Select SOC when CMPA equal to TBPRD
EPwm6Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm6Regs.TBPRD = 20*99; // Set period to 65536 counts
// EPwm6Regs.CMPA.bit.CMPA = 0.49*99;
EPwm6Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = 0;
// Set actions

EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A,

// Interrupt where we will change the Compare Values
//
EPwm6Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm6Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm6Regs.ETPS.bit.INTPRD = 01; // Generate INT on every event // up count

//EPWM3 TRIGGERING FOR ADC TRIGGERING
EPwm3Regs.ETSEL.bit.SOCAEN= 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL= 4; // Select SOC when CMPA equal to TBPRD
EPwm3Regs.ETPS.bit.SOCAPRD= 1; // Generate pulse on 1st event
// Set compare A value to 2048 counts
EPwm3Regs.CMPA.bit.CMPA =0.5*2000;
EPwm3Regs.TBPRD =2000; // Set period to 65536 counts
EPwm3Regs.TBCTL.bit.CTRMODE = 0; // up counter

EPwm3Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = 0;
EPwm3Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A,
EPwm3Regs.ETSEL.bit.INTSEL = 4; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = 01;
EDIS;
}


// SetupADCEpwm - Setup ADC EPWM acquisition window
//
void SetupADCEpwm(Uint16 channel)
{
Uint16 acqps;

//
//determine minimum acquisition window (in SYSCLKS) based on resolution
//
// if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
// {
// acqps = 14; //75ns
// }
// else //resolution is 16-bit
// {
// acqps = 79; //320ns=79
// }

//
//Select the channels to convert and end of conversion flag
//
EALLOW;
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin A2 and A3
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 9; //trigger on ePWM2 SOCA/C
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4; //SOC1 will convert pin A2 and A3
AdcaRegs.ADCSOC4CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = 9; //trigger on ePWM2 SOCA/C
AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 4; //end of SOC1 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT2E = 1; //enable INT2 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 0; //SOC1 will convert pin A2 and A3
AdcbRegs.ADCSOC1CTL.bit.ACQPS = 79; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 9; //trigger on ePWM2 SOCA/C
// AdcaRegs.ADCINTSEL3N4.bit.INT3SEL = 1; //end of SOC1 will set INT1 flag
// AdcaRegs.ADCINTSEL3N4.bit.INT3E = 1; //enable INT2 flag
// AdcaRegs.ADCINTFLGCLR.bit.ADCINT3 = 1; //make sure INT2 flag is cleared
AdcbRegs.ADCINTSEL1N2.bit.INT2SEL = 4; //end of SOC1 will set INT1 flag
AdcbRegs.ADCINTSEL1N2.bit.INT2E = 1; //enable INT2 flag
AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
EDIS;
}

// End of file
//

Hi Joseph, 

I am trying to change the clocks in the code. Meanwhile, I have also tried the code given in Controlsuite for adcsoccontinuous, still ADC is showing zero values. This is the code.

//###########################################################################
//
// FILE: adc_soc_continuous_cpu01.c
//
// TITLE: ADC continuous self-triggering for F2837xD.
//
//! \addtogroup cpu01_example_list
//! <h1> ADC Continuous Triggering (adc_soc_continuous)</h1>
//!
//! This example sets up the ADC to convert continuously, achieving maximum
//! sampling rate.\n
//!
//! After the program runs, the memory will contain:
//!
//! - \b AdcaResults \b: A sequence of analog-to-digital conversion samples
//! from pin A0. The time between samples is the minimum possible based on the
//! ADC speed.
//
//###########################################################################
// $TI Release: F2837xD Support Library v210 $
// $Release Date: Tue Nov 1 14:46:15 CDT 2016 $
// $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"

//
// Function Prototypes
//
void ConfigureADC(void);
void SetupADCContinuous(Uint16 channel);

//
// Defines
//
#define RESULTS_BUFFER_SIZE 256 //buffer for storing conversion results
//(size must be multiple of 16)

//
// Globals
//
Uint16 AdcaResults[RESULTS_BUFFER_SIZE];
Uint16 resultsIndex;

void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
InitGpio(); // Skipped for this example

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
InitPieVectTable();

//
// Configure the ADC and power it up
//
ConfigureADC();

//
// Setup the ADC for continuous conversions on channel 0
//
SetupADCContinuous(0);

//
// Enable global Interrupts and higher priority real-time debug events:
//
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

//
// Initialize results buffer
//
for(resultsIndex = 0; resultsIndex < RESULTS_BUFFER_SIZE; resultsIndex++)
{
AdcaResults[resultsIndex] = 0;
}
resultsIndex = 0;

//
// take conversions indefinitely in loop
//
do
{
//
//enable ADCINT flags
//
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;
AdcaRegs.ADCINTSEL1N2.bit.INT2E = 1;
AdcaRegs.ADCINTSEL3N4.bit.INT3E = 1;
AdcaRegs.ADCINTSEL3N4.bit.INT4E = 1;
AdcaRegs.ADCINTFLGCLR.all = 0x000F;

//
//initialize results index
//
resultsIndex = 0;

//
//software force start SOC0 to SOC7
//
AdcaRegs.ADCSOCFRC1.all = 0x00FF;

//
//keep taking samples until the results buffer is full
//
while(resultsIndex < RESULTS_BUFFER_SIZE)
{
//
//wait for first set of 8 conversions to complete
//
while(0 == AdcaRegs.ADCINTFLG.bit.ADCINT3);

//
//clear both INT flags generated by first 8 conversions
//
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT3 = 1;

//
//save results for first 8 conversions
//
//note that during this time, the second 8 conversions have
//already been triggered by EOC6->ADCIN1 and will be actively
//converting while first 8 results are being saved
//
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT0;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT1;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT2;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT3;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT4;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT5;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT6;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT7;

//
//wait for the second set of 8 conversions to complete
//
while(0 == AdcaRegs.ADCINTFLG.bit.ADCINT4);

//
//clear both INT flags generated by second 8 conversions
//
AdcaRegs.ADCINTFLGCLR.bit.ADCINT2 = 1;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT4 = 1;

//
//save results for second 8 conversions
//
//note that during this time, the first 8 conversions have
//already been triggered by EOC14->ADCIN2 and will be actively
//converting while second 8 results are being saved
//
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT8;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT9;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT10;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT11;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT12;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT13;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT14;
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT15;
}

//
//disable all ADCINT flags to stop sampling
//
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 0;
AdcaRegs.ADCINTSEL1N2.bit.INT2E = 0;
AdcaRegs.ADCINTSEL3N4.bit.INT3E = 0;
AdcaRegs.ADCINTSEL3N4.bit.INT4E = 0;

//
//at this point, AdcaResults[] contains a sequence of conversions
//from the selected channel
//

//
//software breakpoint, hit run again to get updated conversions
//
asm(" ESTOP0");
}while(1);
}

//
// ConfigureADC - Write ADC configurations and power up the ADC for both
// ADC A and ADC B
//
void ConfigureADC(void)
{
EALLOW;

//
//write configurations
//
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

//
//Set pulse positions to late
//
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;

//
//power up the ADC
//
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;

//
//delay for 1ms to allow ADC time to power up
//
DELAY_US(1000);

EDIS;
}

//
// SetupADCContinuous - setup the ADC to continuously convert on one channel
//
void SetupADCContinuous(Uint16 channel)
{
Uint16 acqps;

//
//determine minimum acquisition window (in SYSCLKS) based on resolution
//
if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
{
acqps = 14; //75ns
}
else //resolution is 16-bit
{
acqps = 63; //320ns
}

EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC1CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC2CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC3CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC4CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC5CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC6CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC7CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC8CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC9CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC10CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC11CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC12CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC13CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC14CTL.bit.CHSEL = channel; //SOC will convert on channel
AdcaRegs.ADCSOC15CTL.bit.CHSEL = channel; //SOC will convert on channel

AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC4CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC5CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC6CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC7CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC9CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC10CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC11CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC12CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC13CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC14CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles
AdcaRegs.ADCSOC15CTL.bit.ACQPS = acqps; //sample window is acqps +
//1 SYSCLK cycles

AdcaRegs.ADCINTSEL1N2.bit.INT1E = 0; //disable INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT2E = 0; //disable INT2 flag
AdcaRegs.ADCINTSEL3N4.bit.INT3E = 0; //disable INT3 flag
AdcaRegs.ADCINTSEL3N4.bit.INT4E = 0; //disable INT4 flag

AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 0;
AdcaRegs.ADCINTSEL1N2.bit.INT2CONT = 0;
AdcaRegs.ADCINTSEL3N4.bit.INT3CONT = 0;
AdcaRegs.ADCINTSEL3N4.bit.INT4CONT = 0;

AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 6; //end of SOC6 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 14; //end of SOC14 will set INT2 flag
AdcaRegs.ADCINTSEL3N4.bit.INT3SEL = 7; //end of SOC7 will set INT3 flag
AdcaRegs.ADCINTSEL3N4.bit.INT4SEL = 15; //end of SOC15 will set INT4 flag

//
//ADCINT2 will trigger first 8 SOCs
//
AdcaRegs.ADCINTSOCSEL1.bit.SOC0 = 2;
AdcaRegs.ADCINTSOCSEL1.bit.SOC1 = 2;
AdcaRegs.ADCINTSOCSEL1.bit.SOC2 = 2;
AdcaRegs.ADCINTSOCSEL1.bit.SOC3 = 2;
AdcaRegs.ADCINTSOCSEL1.bit.SOC4 = 2;
AdcaRegs.ADCINTSOCSEL1.bit.SOC5 = 2;
AdcaRegs.ADCINTSOCSEL1.bit.SOC6 = 2;
AdcaRegs.ADCINTSOCSEL1.bit.SOC7 = 2;

//
//ADCINT1 will trigger second 8 SOCs
//
AdcaRegs.ADCINTSOCSEL2.bit.SOC8 = 1;
AdcaRegs.ADCINTSOCSEL2.bit.SOC9 = 1;
AdcaRegs.ADCINTSOCSEL2.bit.SOC10 = 1;
AdcaRegs.ADCINTSOCSEL2.bit.SOC11 = 1;
AdcaRegs.ADCINTSOCSEL2.bit.SOC12 = 1;
AdcaRegs.ADCINTSOCSEL2.bit.SOC13 = 1;
AdcaRegs.ADCINTSOCSEL2.bit.SOC14 = 1;
AdcaRegs.ADCINTSOCSEL2.bit.SOC15 = 1;
EDIS;
}

//
// End of file
//

Thanks Joseph,
ADC started working. I have modified the clocks, also I came to know that system clock should be always set to 200MHzand ADC CLK to 50 MHz, any mismatch will imbalance the system and ADC will not work.
Thanks