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TMS320F28335: double dsp communicating through mcbsp interface leading dsp down

huizhao liu
Prodigy 10 points
Part Number: TMS320F28335


I am engaging an UPS development project,in which I use double 28335 DSP as the controller.These two DSPs communicate through MCBSP.

I am encounting an problem that one dsp can not receive message from the other DSP.I tried to reintial mcbsp peripheral,it does function;but sometimes 

the DSP can be down.The Mcbsp initial subrootine I used as follow,

EALLOW;
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // GPIO58 is MCLKRA pin (Comment as needed)
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 is MFSXA pin
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // GPIO59 is MFSRA pin (Comment as needed)


GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA)
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA)
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA)
GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (MCLKRA) (Comment as needed)
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (MFSXA)
GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (MFSRA) (Comment as needed)

GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 3; // Asynch input GPIO20 (MDXA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch input GPIO21 (MDRA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch input GPIO22 (MCLKXA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA) (Comment as needed)
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (MFSXA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA) (Comment as needed)

EDIS;
//*************** RESET MCBSP

McbspaRegs.SPCR2.bit.FRST=0; // Frame Sync generator reset
McbspaRegs.SPCR2.bit.GRST=0; // Sample Rate generator Reset
McbspaRegs.SPCR2.bit.XRST=0; // Transmitter reset
McbspaRegs.SPCR1.bit.RRST=0; // Receiver reset

McbspaRegs.SPCR1.all=0x0000; //loopback disable, right justify,
McbspaRegs.SPCR1.bit.CLKSTP = 0; //2014.4.4

McbspaRegs.PCR.all=0x0000;
McbspaRegs.PCR.bit.CLKXM =1; //Vivian20140409
McbspaRegs.PCR.bit.CLKRM =0;



McbspaRegs.PCR.bit.SCLKME = 0; //vivian20140404
McbspaRegs.SRGR2.bit.CLKSM =1;//Vivian20140409

McbspaRegs.SRGR2.bit.GSYNC=1;//vivian20140404


McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay
McbspaRegs.PCR.bit.CLKRP = 0;//Vivian20140409

McbspaRegs.PCR.bit.FSRM = 0;
McbspaRegs.PCR.bit.FSRP=0;//20140404 high active
McbspaRegs.PCR.bit.FSXP=0; ///20140409 vivian high active


McbspaRegs.SRGR2.bit.FSGM = 0;
McbspaRegs.PCR.bit.FSXM=1;/////////vivian 20140409


McbspaRegs.SRGR1.all= 0x0F; // Frame Width = 1 CLKG period, CLKGDV=16 //Ethan 2014.5.5

McbspaRegs.RCR2.bit.RDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)


McbspaRegs.RCR2.bit.RFIG = 1; //Ethan 2014.4.29
McbspaRegs.XCR2.bit.XFIG = 1;

McbspaRegs.RCR2.bit.RPHASE=0;/////vivian 20140404
McbspaRegs.RCR1.bit.RFRLEN1 =0; /// 2014.4.24 1 word
McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word //Ethan 2014.4.30


McbspaRegs.XCR2.bit.XPHASE=0;/////vivian 20140409
McbspaRegs.XCR1.bit.XFRLEN1 =0; /// 2014.4.24 1 word
McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word //Ethan 2014.4.30

McbspaRegs.SPCR1.bit.RINTM=0;
McbspaRegs.MFFINT.bit.RINT = 1; // Enable Receive Interrupts

McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
// delay_loop();
clkg_delay_loop();
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset

Other words, is there any reference design of double DSP communicaiting through MCBSP interface?

  • 0
    Guru 30330 points

    Huizhao,

    I have a few questions that should help us find the root of the problem

    1. Have you ensured that the Master device is transmitting the proper data?
    2. Is the data corrupted on the slave device?
    3. How is the data corrupted? Is it shifted? off by one word?
    4. When does the corruption of the data occur? Always? after an event? after some random amount of time?
    5. Ensure that your connections between the two devices are correct. You need to make sure that the master data output pin is connected to the slave data input pin. Refer to the Clock stop mode section for the wiring of the McBSP while in Master and slave mode.

    Side note: please avoid posting large chunks of code in the plain text editor.There is a "SyntaxHighlighter" tool that will allow you to insert formatted code with syntax highlighting. Please check the "collapse" checkbox. This helps make the threads easier to use. I will edit your post showing how code with SyntaxHighlighter looks.

    Thanks,
    Mark

  • 0 in reply to Mark Labbato
    Guru 30330 points
    Huizhao,

    It has been a few days since your post. I am going mark this thread closed. If you are still having issues, please post additional information and we can go from there.

    Thanks,
    Mark