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F28M35H52C: Concerto DIM100 Reference Design FTDI chip

Calvin Taylor25
Prodigy 170 points
Part Number: F28M35H52C


Hi,

I'm using the F28M35H52C in a design, and using the Concerto reference design as a, well, a reference design. :)

The FTDI chip on the Concerto reference design is an FT2232H, and includes an EEPROM as well as a quad nand gate hooked up to some GPIOs. Is there a document that describes how to program the EEPROM, what the GPIOs are configured to do, etc.?

Where might I find such a document?

Calvin

  • 0
    TI__Guru* 80640 points

    Calvin,

    The method to program the EEPROM of the FTDI to behave as the XDS100v2 + UART is documented here:

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/252873/889381#889381 

    In terms of the NAND gate, this device utilizes optional JTAG pins EMU0/1 and as such requires they be held in a correct state during power up/boot up of the FTDI before it can assume control.  The NAND gate implementation on the control card satisfies this, so that everything will come out of reset in a stable manner. 

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 170 points

    Much appreciated! Thanks!

    It seems like this is a common enough thing that there should be some documentation in the tools and/or support page for the processor and/or Concerto Board, doesn't it?

    Calvin

  • 0 in reply to MatthewPate
    Prodigy 170 points
    Thanks Matthew,

    In that case, I've a question: EMU0/1 are bidirectional signals, providing boot mode info into the processor, and getting trace data out. However, in the CONCERTO_DIMM100, the digital isolators that the signal feeds into are uni-directional. Can you explain what's going on here?

    Thanks much,

    Calvin
  • 0 in reply to Calvin Taylor25
    TI__Guru* 80640 points
    Calvin,
    Good question; historically C2000 MCUs do not have a on-chip trace logic that would use the EMU0/1 pins as on other TI MCU/DSPs. As for the ARM side, there is an ITM on this device, but it routes its signals through other GPIOs, rather than the JTAG header.

    For the previous question, I agree that this should have some better documentation around it; my general understanding is that at the time we were trying to cost reduce with the NAND gates vs what is found inside an off the shelf emulator. I need to check if I can find the precise reason, i.e. FTDI takes x ns to boot, and the signal needs to be steady before that, etc.

    Best,
    Matthew