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Hi,
I have the following Bourns encoder
connected to the launchpad GPIO24, GPIO25 as per the following schematic:
I am using the following code to read the encoder position:
// Encoder is connected to QEP_B
// ENC_A is connected to EQEP2A (GPIO24)
// ENC_B is connected to EQEP2B (GPIO25)
void init_eqep2_gpio(void)
{
EALLOW;
// Enable internal pull-up for the selected pins
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EQEP2A)
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EQEP2B)
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EQEP2I)
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EQEP2S)
// Inputs are synchronized to SYSCLKOUT by default.
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A)
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B)
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I)
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S)
// Configure eQEP-1 pins using GPIO regs
// This specifies which of the possible GPIO pins will be eQEP1 functional
// pins.
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S
EDIS;
}
void init_qcap(void)
{
EQep2Regs.QUPRD = 800000; // Unit Timer for 100Hz at 80 MHz SYSCLKOUT
EQep2Regs.QDECCTL.bit.QSRC = 0; // QEP quadrature count mode
// EQep2Regs.QDECCTL.bit.SOEN = 1; // Enable position compare
EQep2Regs.QEPCTL.bit.FREE_SOFT = 2;
EQep2Regs.QEPCTL.bit.PCRM = 1; // PCRM = 1 mode - QPOSCNT reset on max position
EQep2Regs.QPOSMAX = 0x32; // max value is 50
EQep2Regs.QEPCTL.bit.QPEN = 1; // QEP enable
EQep2Regs.QCAPCTL.bit.UPPS = 5; // 1/32 for unit position
EQep2Regs.QCAPCTL.bit.CCPS = 6; // 1/64 for CAP clock
EQep2Regs.QCAPCTL.bit.CEN = 1; // QEP Capture Enable
}
void main(void)
{
uint16_t i = 0, r = 0, pos;
InitSysCtrl();
init_mcbspa_gpio(); /* setup gpio for mcbspa/spi */
init_eqep2_gpio(); /* setup gpio for encoder */
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.DINTCH1 = &isr_dma_ch1; /* Tx ISR DMA CH1 INT7.1 */
EDIS;
init_qcap();
dma_init(); /* dma initialization alone */
setup_lcd_pins(); /* setup LCD RESET, D/C pins */
ssd1306_reset(); /* Reset LCD */
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; /* Enable PIE block */
PieCtrlRegs.PIEIER7.bit.INTx1 = 1; /* Enable PIE Group 7 INT1(DMA CH1) */
IER = 0x40; /* Enable CPU INT Group 7 */
EINT; /* Enable Global Interrupts */
while (1) {
pos = (int) EQep2Regs.QPOSCNT;
rad_graph(pos);
DELAY_US(2000);
}
}
I do see values being changed in the QPOSCNT register as can be seen in the debugger view.
I have a LCD also connected to the McBSP peripheral, which displays the QPOSCNT value.
The value I can see changing on the display as well, but the values seem to jump around with no relation eg: rotating the encoder the jump seem to be with much large values for a single turn of the encoder. Wondering how to address the issue ?
Is the issue addressable with the UPPS and the CCPS bits in the QCAPCTL register ?
ie :
EQep2Regs.QCAPCTL.bit.UPPS = 5; // 1/32 for unit position
EQep2Regs.QCAPCTL.bit.CCPS = 6; // 1/64 for CAP clock
GPIO24 and GPIO25 are configured for the encoder alone and nothing else.
I have a scope connected to GPIO25, I see a waveform on the pin, even when the encoder is not being turned, as seen in the picture:
confused on the situation and hence my questions:
1. I am confused why the QPOSCNT value jumps around ? Is it probably due to the timer being configured incorrectly ?
2. Why is there a signal being generated by the controlled on the encoder input line ?
Any thoughts ?
Thanks,
Manu
Hi Manu,
Thank you for explaining your issue so thoroughly. I understand your issue now.
Regarding your registers window issue within CCS, it probably doesn't make a difference, but I often use the expressions window to view specific registers/bits. That way you can type in the specific register you're wanting to look at and focus on it, see below for what I mean.
As of right now, I'm not sure why you're facing the stalling issue when under-flowing, but not over-flowing.I will let you know if I come up with a good explanation to provide (consulting colleagues and other resources). As I've stated before, your use-case is a little different than what we usually hear. I believe resetting at an underflow/overflow occurrence is often desired.
CCS may be related, but I'm not really convinced since you have the LCD display showing the issue as well. Running your program stand-alone (from flash) may give a better idea if it's related or not.
For now I think further testing/debugging on your side would help, focusing on what is really going on when an underflow interrupt occurs. You could place a break-point in your underflow ISR and see what goes on afterwards (i.e. does it do what it's supposed to and exit OK). Checking the QEP status register (QEPSTS) before and after the issue occurs may give some insight as well.
Does this issue happen anytime a underflow condition / interrupt occurs or only after a prior overflow condition? Some further tests like this may give you a better idea of what's going on.
Best,
Kevin
Hi Kevin,
Managed to get a snapshot of the eQEP2 registers when it crashes, the following code:
/* INT5.2 is eQEP2 */
__interrupt void isr_eqep2(void)
{
EALLOW;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; /* Interrupt ACK */
EQep2Regs.QCLR.bit.INT = 1; /* clear global interrupt */
if (EQep2Regs.QFLG.bit.PCO == 1) {
EQep2Regs.QCLR.bit.PCO = 1; /* position counter has overflown */
EQep2Regs.QPOSCNT = EQep2Regs.QPOSMAX; /* reset position counter to max */
}
if (EQep2Regs.QFLG.bit.PCU == 1) {
EQep2Regs.QCLR.bit.PCU = 1; /* position counter has underflown */
EQep2Regs.QPOSCNT = 0; /* reset position counter to init */
}
if (EQep2Regs.QFLG.bit.PCM == 1) {
EQep2Regs.QCLR.bit.PCM = 1; /* position counter match condition */
}
EDIS;
return;
}
void init_qcap(void)
{
EQep2Regs.QDECCTL.bit.QSRC = 0; /* QEP quadrature count mode */
EQep2Regs.QDECCTL.bit.XCR = 1; /* 1x resolution, count rising edge */
EQep2Regs.QPOSINIT = 0; /* Initial position is 0 */
EQep2Regs.QPOSMAX = 400; /* max value is 400 */
EQep2Regs.QPOSCMP = 1; /* compare with this value */
EQep2Regs.QEPCTL.bit.FREE_SOFT = 0; /* TMR, CNTR unaffected by suspend */
EQep2Regs.QEPCTL.bit.PCRM = 1; /* QPOSCNT reset mode */
EQep2Regs.QEPCTL.bit.QCLM = 0; // Latch on unit time out
EQep2Regs.QEINT.bit.PCO = 1; /* counter overflow int enable */
EQep2Regs.QEINT.bit.PCU = 1; /* counter underflow int enable */
EQep2Regs.QCAPCTL.bit.UPPS = 1; // for UPEVNT Generation
EQep2Regs.QCAPCTL.bit.CCPS = 6; // 1/64 for CAP clock (input 40 Hz)
EQep2Regs.QPOSCTL.bit.PCE = 1; /* enable position compare unit */
EQep2Regs.QEPCTL.bit.QPEN = 1; /* QEP enable */
EQep2Regs.QCAPCTL.bit.CEN = 1; /* QEP Capture Enable */
}
The encoder is rotated clockwise to increase QPOSCNT:
Still increasing:
Now, encoder rotated to decrease:
Still decreasing:
And crashed:
QFLG = 0x80F, I don't seem to handle PHE and PCE in the interrupt handler
But, what's to be done when there is Position counter error interrupt flag or Quadrature phase error interrupt flag or QDC.
But the more interesting issue is that, QEINT changes from 0x60 to 0x68.
The only place where QEINT is modified is:
EQep2Regs.QEINT.bit.PCO = 1; /* counter overflow int enable */
EQep2Regs.QEINT.bit.PCU = 1; /* counter underflow int enable */within init_qcap()
I therefore wonder, what's happening.
Hope that would be enough to expose what's happening at register level, during the crash. Also, after the crash, the display gets completely garbled.
The more interesting aspect is, to fix the crash is to
/* INT5.2 is eQEP2 */
__interrupt void isr_eqep2(void)
{
EALLOW;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; /* Interrupt ACK */
EQep2Regs.QCLR.bit.INT = 1; /* clear global interrupt */
if (EQep2Regs.QFLG.bit.PCO == 1) {
EQep2Regs.QCLR.bit.PCO = 1; /* position counter has overflown */
EQep2Regs.QPOSCNT = EQep2Regs.QPOSMAX; /* reset position counter to max */
}
if (EQep2Regs.QFLG.bit.PCU == 1) {
EQep2Regs.QCLR.bit.PCU = 1; /* position counter has underflown */
// EQep2Regs.QPOSCNT = 0; /* reset position counter to init */
}
if (EQep2Regs.QFLG.bit.PCM == 1) {
EQep2Regs.QCLR.bit.PCM = 1; /* position counter match condition */
}
EDIS;
return;
}Everything is fine in this situation, except that during an underflow, QPOSCNT becomes QPOSMAX.
Wonder, what's going on. Maybe you have more answers/thoughts ?
Thanks,
Manu
Hi Kevin,
Thanks for sharing the thought. I was overjoyed for a moment that we probably found a solution to the landmine. The joy seemed to have short lived.
Yes, touching the QPOSCNT is what the controller does not like on anyway, especially in the Underflow situation.
1. The first thought, I tried out; Setting QEPCTL::FREE_SOFT = 1.
(without modifying QPOSCNT=0 in the Underflow Interrupt situation. If QPOSCNT is modified, the crash still happens)
In this situation, what happens in the Underflow situation is QPOSCNT goes back to QPOSMAX
2. Position Compare Shadow Mode:
The Shadow Mode loads the shadowed value into QPOSCMP, rather than QPOSCNT, No ?
Looking at the diagram, I think that's what could possibly be. I could be likely mistaken though.
I did try out the same, without touching QPOSNT at all, since landmines are laid out there.
/* INT5.2 is eQEP2 */
__interrupt void isr_eqep2(void)
{
EALLOW;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; /* Interrupt ACK */
if (EQep2Regs.QFLG.bit.INT == 1)
EQep2Regs.QCLR.bit.INT = 1; /* clear global interrupt */
if (EQep2Regs.QFLG.bit.PCO == 1) {
EQep2Regs.QCLR.bit.PCO = 1; /* position counter has overflown */
EQep2Regs.QPOSCNT = EQep2Regs.QPOSMAX; /* reset position counter to max */
}
if (EQep2Regs.QFLG.bit.PCU == 1) {
EQep2Regs.QCLR.bit.PCU = 1; /* position counter has underflown */
// EQep2Regs.QPOSCNT = 0; /* reset position counter to init */
}
if (EQep2Regs.QFLG.bit.WTO == 1) /* Watchdog timeout interrupt */
EQep2Regs.QCLR.bit.WTO = 1;
if (EQep2Regs.QFLG.bit.UTO == 1) /* Unit time out interrupt */
EQep2Regs.QCLR.bit.UTO = 1;
if (EQep2Regs.QFLG.bit.PCR == 1) /* Position-compare ready interrupt */
EQep2Regs.QCLR.bit.PCR = 1;
if (EQep2Regs.QFLG.bit.PCM == 1) /* position counter match condition */
EQep2Regs.QCLR.bit.PCM = 1;
if (EQep2Regs.QFLG.bit.PCE == 1) /* Position counter error */
EQep2Regs.QCLR.bit.PCE = 1;
if (EQep2Regs.QFLG.bit.PHE == 1) /* Quadrature phase error */
EQep2Regs.QCLR.bit.PHE = 1;
if (EQep2Regs.QFLG.bit.QDC == 1) /* Quadrature Direction Change */
EQep2Regs.QCLR.bit.QDC = 1;
EDIS;
}
void init_qcap(void)
{
EQep2Regs.QDECCTL.bit.QSRC = 0; /* QEP quadrature count mode */
EQep2Regs.QDECCTL.bit.XCR = 1; /* 1x resolution, count rising edge */
EQep2Regs.QPOSINIT = 0; /* Initial position is 0 */
EQep2Regs.QPOSMAX = 400; /* max value is 400 */
EQep2Regs.QPOSCMP = 0; /* compare with this value */
EQep2Regs.QPOSCTL.bit.PCSHDW = 1; // Position compare shadow enable
EQep2Regs.QPOSCTL.bit.PCLOAD = 1; // Load when QPOSCNT = QPOSCMP
EQep2Regs.QEPCTL.bit.FREE_SOFT = 1; /* TMR, CNTR unaffected by suspend */
EQep2Regs.QEPCTL.bit.PCRM = 1; /* QPOSCNT reset mode */
EQep2Regs.QEPCTL.bit.QCLM = 0; // Latch on unit time out
EQep2Regs.QEINT.bit.PCO = 1; /* counter overflow int enable */
EQep2Regs.QEINT.bit.PCU = 1; /* counter underflow int enable */
EQep2Regs.QCAPCTL.bit.UPPS = 1; // for UPEVNT Generation
EQep2Regs.QCAPCTL.bit.CCPS = 6; // 1/64 for CAP clock (input 40 Hz)
EQep2Regs.QPOSCTL.bit.PCE = 1; /* enable position compare unit */
EQep2Regs.QEPCTL.bit.QPEN = 1; /* QEP enable */
EQep2Regs.QCAPCTL.bit.CEN = 1; /* QEP Capture Enable */
}
Is that what you intended, or did I miss something out ? Have a very strange feeling that something is amiss.
Thanks,
Manu
Hi Kevin,
Let me take this in different chunks. Slightly confusing for me.
I have 2 and only 2 interrupts and both of them in 2 different groups as well, to be precise:
(1) DMA CH1 IRQ In Group 7
(2) eQEP2 IRQ in Group 5
and nothing more than that.
Interrupt prioritization according to
the priorities are fixed for each of the groups.
The questions, that loom in my mind are:
(1) I am not using a nested interrupt within the group, so does the issue of nested interrupt affect the given context ?
(2) If I am mistaken, is there a specific way to change the priority assigned to the different groups. At the moment I am unable to find how to change the priority in this context. Can you please clarify ?
Or did you mean something else ?
I am a bit really confused now. Would be nice to get some helping hand/thoughts here.
Thanks,
Manu
