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TMS320F28379D: ADCCLK Period

Troy Tharpe
Prodigy 20 points
Part Number: TMS320F28379D


Hello,
My name is Troy and my partner and I are using the TMS320F28379D launchpad for prototyping a senior design project, specifically the on board ADC.
We are interested in running the ADC in 16 bit differential mode as fast as possible. The ADCCLK is tied to SYSCLK through a divide, and has a divide by 1 option listed (meaning we originally thought that the ADC clk could run at 200MHz).
However, I saw in sprs880j.pdf on page 103 that the minimum sample and hold time = 320ns, and that 1 ADCCLK cycle must = Tsh = 320ns 
Is this spec accurate? If so is there any way to run the ADC faster than 3.125MHz and still get correct operation?
Thank you in advanced for the clarification.
  • 0
    TI__Guru 55700 points

    Troy,

    I have notified our ADC experts about your post. Please expect a response from them on / before Oct 9, 2018.

    Regards,
    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Guru 60865 points

    Hi Troy,

    The summary page of the datasheet lists the maximum 16-bit ADC sample rate as 1.1MSPS, which is accurate.

    Per the operating conditions table:

    You can see that the maximum ADCCLK rate is 50MHz, so normally the SYSCLK to ADCCLK divider will be set to /4.  

    The S+H is always clocked by SYSCLK regardless of the SYSCLK to ADCCLK divider. The footnote in questions is saying that the S+H must always be at least as long as one ADCCLK.  e.g. if SYSCLK is 50MHz and ADCCLK is 6.25 MHz then 1 ADCCLK cycle is 160ns.  The S+H would need to be set to be at least 160ns even if less than 160ns would otherwise be OK (12-bit minimum S+H is 75ns).  This isn't a condition you are going to run into unless you are trying to run the ADC very slow.    

    Note that to get good results with minimum S+H time (and thus maximum sample rate) you need to drive the ADC input with a low impedance + high bandwidth source (usually an op-amp). Otherwise you need to select an appropriately long S+H time such that the input driver can settle to 16+1 bits in the allocated S+H time.

    Once you know the SYSCLK, ADCCLK, and S+H time, you can determine the exact ADC timings using the "ADC Timing Diagrams" section of the datasheet.  

  • 0 in reply to Manoj Santha Mohan
    TI__Mastermind 38900 points

    Hi Troy,

    The ADCCLK for the TMS320F28379D is rated to operate at a max frequency of 50MHz.  The ADCCLK is prescaled from SYSCLK.  The launchpad is operating at 200MHz and in order for the ADC to operate properly at 50Mhz, you should set your ADC prescaler to a value of 6 (divide by 4 from SYSCLK).  See decription of register ADCCTL2 (PRESCALE). 

    In 16-bit mode, the minimum sample and hold time for the ADC is 320ns.  Sample and hold time is (ACQPS+1)*SYSCLK period.  If SYSCLK is set at 200Mhz, ACQPS value to meet the minimum sample and hold time is 63 [(320ns/(1/200MHz)) - 1].  See description of registers ADCSOCxCTL (ACQPS) for more details.  Note that the sample and hold time is not a function by ADCCLK, but by ACQPS setting and SYSCLK.  Also note that maximum throughput in 16-bit mode (with the 320ns minimum sample and hold time) is at 1.1MSPS.  You will get inaccurate conversion results if sample and hold time is less than this value.  You can interleave conversions on the different ADC modules if you want to attain higher throughput overall (up to 4.4 MSPS).

    Hope this helps clarify your questions.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Prodigy 20 points

    Hi Joseph,

    Thanks for the quick reply, that definitely cleared things up.

    My mistake was treating the SH time as equal to the ADC clock period due to the footnote at the bottom of the table. With an interleaved throughput of 4.4 MSPS our design should work fine.

    Thank you,

    Troy