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TMS320F28062: SPI SPISTE to SPICLK timing

Sebastien Prince
Prodigy 20 points
Part Number: TMS320F28062


I have my SPI configured with Clock Polarity to 0 and Clock Phase to 1. From the datasheet (TMS320F2806x Piccolo™ Microcontrollers) at page 107, the delay between SPISTE falling and SPICLK should be the same time as the SPI clock period. But from my measurement it is alway twice that value. For the capture exemple I measured a SPI clock period of 0.676us and the SPISTE to SPICLK time is around twice that time at 1.32us. I observe the same thing even if I change the SPI clock.

I don't know if I missed some details on that.

Regards,

Sebastien

  • 0
    TI__Guru 60865 points
    Hi Sebastian,

    You are talking about timing '23' in "Table 6-36. SPI Master Mode External Timing (Clock Phase = 1)"?

    The MIN value is quoted as 1 SPICLK - 10ns. But since this is a MIN value, the actual value can be longer.

    If you look at the corresponding slave timing, the module has a minimum value to meet setup timings, but there isn't a maximum value. This would indicate that the communication will work as long as the time between those two edges is long enough (but too long shouldn't be a problem).
  • 0 in reply to Devin Cottier
    Prodigy 20 points

    Hi Devin,

    Thanks for the answer

    Regards,