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CCS/TMS320F28377D: Loop current in ADC

Hui Chen
Intellectual 880 points

Part Number: TMS320F28377D
Other Parts Discussed in Thread: AMC1100, TINA-TI

Tool/software: Code Composer Studio

Hello everyone！

I encountered strange phenomenon in the ADC process I used in 28377D. I used to hink that ADCs were high impedance inputs, but now there are two circuit channel that represent differential ADCs forming a loop current that affects actual sampling.

I realize NTC voltage sampling through the voltage divider circuit, as shown in the figure below. The sampling circuit is located in another circuit board, and is connected by a connector in the middle. Analog voltage VREFHI A ~ D connects VDDA 3.3V. VREFLO A ~ D connects AGND. AGND connects GND through 0R.

I only used 3 differential inputs for this system. The 2 way is NTC voltage sampling. Two out of 100 PCBs with problems, differential input pins ADC-A 0 and ADC-A1, ADC-A2 and ADC-A3, form currents of uniform magnitude in opposite directions.

The size of the current varies from time to time, most of which is 0.3mA. There are several other characteristics:

1, the loop current may appear after a few minutes of power up, or a power up.
2, one of the boards was good before, and now it appears.
3, we are configured to 12bit sampling, or turn off ADC initialization, can not eliminate loop current.
4, normally, port voltage is 2.5V. Occasionally we can see port voltage trying to restore 2.5V, but we are immediately pulled across.
5. We removed the capacitor and clamp diode, there is a backflow, you can be sure that the current is from the DSP internal flow.
What is the cause of this phenomenon?

  • 0
    TI__Guru 60865 points
    Hi Tina,

    The ADC inputs are not high impedance, but are instead switched-capacitor circuits. You can see the input model for these circuits in the datasheet sections "Table 5-47. Differential Input Model Parameters" and "Table 5-48. Single-Ended Input Model Parameters".

    To get some idea of how to calculate setting of the ADC input see the section "Choosing an Acquisition Window Duration" in the TRM. The F28004x device actually has an updated version of this section that is improved (and the F2837xD device will get its section updated soon when a new version of the document is published).

    I'm not sure if this explains your observations.

    Some other notes:
    Channels A0 and A1 (and B1) have a parasitic pull-down due to the muxed buffered-DAC. This could result in ~50uA of parasitic current, which is less than you observe.

    Are you using differential mode on channels A0/A1 and A2/A3? Based on the circuit above I don't think this will work due to the common-mode voltage requirement of the fully-differential ADC inputs. See this link for some explanation of the various ADC input types: training.ti.com/ti-precision-labs-adcs-sar-adc-input-types.

    VREFHI supplied directly by VDDA is not recommended if you are concerned with analog performance.

    The ADC inputs have internal protection diodes which can conduct current. This should only occur if the input is 0.3V below VSSA or 0.3V above VDDA.
  • 0 in reply to Devin Cottier
    Intellectual 880 points

    Thank you for your reply.I want to know 28377D ADC is fully differential input or true differential input. From datasheet table 4-41,we can get 28377d is fully differential  input and (VinP - VinN) must be in Vref/2±0.05 range.

    1、How to understand the meaning of this"The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO"?

    2、But why  we use AMC1100 which output common mode voltage is 1.29V can get  the correct measurement results?

    3、When we measure the NTC voltage, A1and A3 is connected to GND, and A0 and A2 is usually 2.5V. Why can we almost get  correct measurements in hundreds of PCB.?

    4、If I modify the circuit diagram, add a resistor. The negative  input pin of differential input is higher 0.6V than VSSA . Can the circuit work properly?

    Looking forward to receiving your reply.

  • 0 in reply to Devin Cottier
    Intellectual 880 points

    The following figure is found on the latest 28377 data handbook. However, the address of the register was not found.Does this resistances have anything to do with the loop current?

  • 0 in reply to Devin Cottier
    Intellectual 880 points

    Why need to fix the common mode voltage to REF/2 in the fully-differential ADC ?( VINP+VIN-) /2+Vnoise will often exceed the  50mV range. is it  very weak to resist common mode interference?

  • 0 in reply to Hui Chen
    TI__Guru 60865 points
    Hi Tina,

    The opens/shorts circuit will not affect the conversion results when not in use and it is not in use unless explicitly enabled.

    Yes, the ADC inputs are fully differential, not truly differential.

    VSSA = ADCINn will not meet the common mode requirements because the common mode will only be exactly VREFHI/2 when ADCINp is exactly VRFEHI. For other voltages there will be systematic common mode error. e.g. if ADCINp is 1V and VREFHI is 2.5V then the common mode will be (1V + 0V)/2 = 0.5V, for a common mode error of 1.25V - 0.5V = 0.75V which is much larger than the specified 0.05V.

    From the above it should also be clear why when the output of your sensor is ~2.5V the sensing more-or-less works, but when it deviates from 2.5V the results start to accumulate error.

    The common mode rejection is specified in the datasheet as 60dB at 1MHz. This will result in 1 LSBs of noise to the conversion output with 1000 LSBs of common mode noise at the input. 1000LSBs is massively noisy. While 1000LSBs = 38mV with VREFHI = 2.5V, this does not mean that if the ADCINcm is VREFHI/2 + 13mV that the CMR will be reduced; the CMR is valid for all valid ADCINcm conditions.

    To transform the Vcm of a signal, the easiest solution is to use a fully-differential op-amp buffer and set the Vocm to the target common mode.
  • 0 in reply to Devin Cottier
    Intellectual 880 points

    Thank you for your reply In my circuit board  VREFHI = 3.3   VREFLO=0.

    I would like to sum up and see if my conclusion is correct.

    1. The reason for the formation of the loop current is unknown.

    2.There is error in differential input mode, but this will not lead to loop current.

    3.The common-mode voltage exceeds the prescribed range due to the error of differential input mode, but only affects the measurement accuracy. Is it because we have low requirements for measurement accuracy and have not found the impact of this problem?

    Finally, if we input the NTC into 12 bit single ended input ADC. AMC1100 is a differential input, but we still single end sampling, and then  differential calculation by program. Can we solve the problem?

  • 0 in reply to Hui Chen
    TI__Guru 60865 points
    Hi Tina,

    1.2. Yes, I don't think we have determined the reason for the loop current. Violating the common mode should not cause the ADC inputs to conduct continuous current. The things that could result in continuous current are a voltage 0.3V above VDDA or 0.3V below VSSA (resulting in clamping current on the ADC input), the parasitic current from the muxed DACs on ADCA0, A1, and B1, and/or normal leakage current on the pins which should be <2uA. Have you tried simulating the circuit in TINA-TI SPICE platform?

    3. Yeah, the primary result of violating the common-mode requirement is reduced accuracy/performance. If the input is typically near 2.5V then the common-mode violation will be less than if the signal swings through the full range.

    There are a couple potential issues with sampling both signals single-ended, then subtracting.
    -If either signal falls below VREFLO or above VREFHI then the ADC will saturate (but only for one half of the calculation, resulting in error)
    -If both signals are on the same ADC they can't be sampled at exactly the same time. You can overcome this by sampling ch1-ch2-ch1 and then averaging the two ch1 samples or you can do something like 1-2-2-1 and then average both if you want an equal number of samples. Alternately, you can sample the two single-ended signals on two different ADCs so that they can be sampled simultaneously.