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TMS320F28034: Software forcing PWM sync

Radey Shouman
Prodigy 190 points

Part Number: TMS320F28034

I am using the PWM5 counter simply to trigger interrupts used to update compare values for PWM1-4.  PWM1-5 are all in up-down count mode.  In order to get the timing right I need a phase offset for PWM5 relative to the other PWM.  Currently I have a procedure that works:

  1. clear PCLKCR0[TBCLKSYNC]
  2. set up PWM registers, including TBPHS nonzero for PWM5
  3. set TBCTL[PHSEN] for PWM5
  4. set PWM1 TBCTL[SYNCOSEL] to 2 for sync output when counter = CMPB
  5. set PWM1 CMPB to 1
  6. set PWM2-5 TBCTL[SYNCOSEL] to 0 for pass through
  7. set PCLKCR0[TBCLKSYNC]
  8. set PWM1 TBCTL[SYNCOSEL] to 0 to disable sync output

This procedure does work:  the counter of PWM5 is set to TBPHS as I expect, counting in the correct direction.

I have tried to use instead a software forced sync as a simpler alternative.  As a test, I set TBCTL[SWFSYNC] for PWM2 immediately after setting PCLKCR0[TBCLKSYNC].

The software force did have the effect of setting PWM5 TBSTS[SYNCI], but it did not cause TBPHS to be loaded to TBCTR.  This was a disappointment.

What am I missing with regard to software forcing PWM sync?

  • 0
    TI__Mastermind 42195 points

    Radey,

    The software sync is only enabled for a SYNCOSEL value of 00. See the excerpt from the TRM below.

    "

    This event is ORed with the EPWMxSYNCI input of the ePWM module.
    SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00.

    "

    Which PWM's SWFSYNC are you setting?

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Prodigy 190 points

    Cody,

    First I tried PWM5, because that seemed simplest.  When that did not work I tried PWM2, which does have SYNCOSEL set to 0.

    PWM2 successfully passes the sync signal down the line when it originates with PWM1.

    regards,

    Radey

  • 0 in reply to Radey Shouman
    TI__Mastermind 42195 points

    Radey,

    in order for a SWFSYNC to take effect you have to setup and enable the sync chain. The full details of how to do that can be found in the ePWM User's Guide. It looks to me like you are trying to setup everything correctly, can you read back the configuration using the memory browser?

    List of stuff you should check:

    • Make sure that you have PHSEN enabled
    • You have a value loaded into TBPHS
    • You have to correctly configure EPWMxSYNCO and EPWNxSYNCI.
    • Additionally, for a SWFSYNC to take effect you have to set SYNCOSEL = 00.


    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Prodigy 190 points
    Cody,

    I have appended a copy of the Registers window for PWM1-5 to the end of this message.

    I would like to reiterate that this configuration works when PWM1 sync on CMPB is used, that is, it causes
    PWM5 TBPHS to be copied to TBCTR. The sole differences are in PWM1 TBCTL (0x202A) and PWM CMPB (1).

    It does not work when PWM2 (or PMW5) software sync is used, the sync bit in TBSTS for PWM5 is set, but TBPHS is not copied. The exact same register configuration for PWM2-PWM5 is used in both the successful and failing cases.

    ePWM1 ePWM1 Registers
    TBCTL 0x200A Time Base Control Register [Memory Mapped]
    TBSTS 0x0001 Time Base Status Register [Memory Mapped]
    TBPHS 0x00000000 Union of TBPHS:TBPHSHR [Memory Mapped]
    TBCTR 0x0379 Time Base Counter [Memory Mapped]
    TBPRD 0x0600 Time Base Period register set [Memory Mapped]
    TBPRDHR 0x0000 Time Base Period High Res Register [Memory Mapped]
    CMPCTL 0x0005 Compare control [Memory Mapped]
    CMPA 0x030A0000 Union of CMPA:CMPAHR [Memory Mapped]
    CMPB 0x0001 Compare B reg [Memory Mapped]
    AQCTLA 0x0060 Action qual output A [Memory Mapped]
    AQCTLB 0x0060 Action qual output B [Memory Mapped]
    AQSFRC 0x0080 Action qual SW force [Memory Mapped]
    AQCSFRC 0x0000 Action qualifier continuous SW force [Memory Mapped]
    DBCTL 0x002B Dead-band control [Memory Mapped]
    DBRED 0x0022 Dead-band rising edge delay [Memory Mapped]
    DBFED 0x0022 Dead-band falling edge delay [Memory Mapped]
    TZSEL 0x0100 Trip zone select [Memory Mapped]
    TZDCSEL 0x0082 Trip zone digital comparator select [Memory Mapped]
    TZCTL 0x0226 Trip zone control [Memory Mapped]
    TZEINT 0x007C Trip zone interrupt enable [Memory Mapped]
    TZFLG 0x0000 Trip zone interrupt flags [Memory Mapped]
    TZCLR 0x0000 Trip zone clear [Memory Mapped]
    TZFRC 0x0000 Trip zone force interrupt [Memory Mapped]
    ETSEL 0xA900 Event trigger selection [Memory Mapped]
    ETPS 0x1101 Event trigger pre-scaler [Memory Mapped]
    ETFLG 0x000C Event trigger flags [Memory Mapped]
    ETCLR 0x0000 Event trigger clear [Memory Mapped]
    ETFRC 0x0000 Event trigger force [Memory Mapped]
    PCCTL 0x0000 PWM chopper control [Memory Mapped]
    HRCNFG 0x0000 HRPWM Config Reg [Memory Mapped]
    HRPWR 0x0000 HRPWM Power Register - N/A on F2806x devices [Memory Mapped]
    HRMSTEP 0x0000 HRPWM MEP Step Register [Memory Mapped]
    HRPCTL 0x0000 High Resolution Period Control [Memory Mapped]
    TBPRDM 0x06000000 Union of TBPRD:TBPRDHR mirror registers [Memory Mapped]
    CMPAM 0x030A0000 Union of CMPA:CMPAHR mirror registers [Memory Mapped]
    DCTRIPSEL 0xAAAA Digital Compare Trip Select [Memory Mapped]
    DCACTL 0x0002 Digital Compare A Control [Memory Mapped]
    DCBCTL 0x0002 Digital Compare B Control [Memory Mapped]
    DCFCTL 0x0000 Digital Compare Filter Control [Memory Mapped]
    DCCAPCTL 0x0000 Digital Compare Capture Control [Memory Mapped]
    DCFOFFSET 0x0000 Digital Compare Filter Offset [Memory Mapped]
    DCFOFFSETCNT 0x0000 Digital Compare Filter Offset Counter [Memory Mapped]
    DCFWINDOW 0x0000 Digital Compare Filter Window [Memory Mapped]
    DCFWINDOWCNT 0x0000 Digital Compare Filter Window Counter [Memory Mapped]
    DCCAP 0x0000 Digital Compare Filter Counter Capture [Memory Mapped]
    ePWM2 ePWM2 Registers
    TBCTL 0x200A Time Base Control Register [Memory Mapped]
    TBSTS 0x0003 Time Base Status Register [Memory Mapped]
    TBPHS 0x00000000 Union of TBPHS:TBPHSHR [Memory Mapped]
    TBCTR 0x0379 Time Base Counter [Memory Mapped]
    TBPRD 0x0600 Time Base Period register set [Memory Mapped]
    TBPRDHR 0x0000 Time Base Period High Res Register [Memory Mapped]
    CMPCTL 0x0005 Compare control [Memory Mapped]
    CMPA 0x02F60000 Union of CMPA:CMPAHR [Memory Mapped]
    CMPB 0x0000 Compare B reg [Memory Mapped]
    AQCTLA 0x0060 Action qual output A [Memory Mapped]
    AQCTLB 0x0060 Action qual output B [Memory Mapped]
    AQSFRC 0x0080 Action qual SW force [Memory Mapped]
    AQCSFRC 0x0000 Action qualifier continuous SW force [Memory Mapped]
    DBCTL 0x002B Dead-band control [Memory Mapped]
    DBRED 0x0022 Dead-band rising edge delay [Memory Mapped]
    DBFED 0x0022 Dead-band falling edge delay [Memory Mapped]
    TZSEL 0x0100 Trip zone select [Memory Mapped]
    TZDCSEL 0x0082 Trip zone digital comparator select [Memory Mapped]
    TZCTL 0x0226 Trip zone control [Memory Mapped]
    TZEINT 0x0000 Trip zone interrupt enable [Memory Mapped]
    TZFLG 0x0000 Trip zone interrupt flags [Memory Mapped]
    TZCLR 0x0000 Trip zone clear [Memory Mapped]
    TZFRC 0x0000 Trip zone force interrupt [Memory Mapped]
    ETSEL 0x0000 Event trigger selection [Memory Mapped]
    ETPS 0x0000 Event trigger pre-scaler [Memory Mapped]
    ETFLG 0x0000 Event trigger flags [Memory Mapped]
    ETCLR 0x0000 Event trigger clear [Memory Mapped]
    ETFRC 0x0000 Event trigger force [Memory Mapped]
    PCCTL 0x0000 PWM chopper control [Memory Mapped]
    HRCNFG 0x0000 HRPWM Config Reg [Memory Mapped]
    HRPCTL 0x0000 High Resolution Period Control [Memory Mapped]
    TBPRDM 0x06000000 Union of TBPRD:TBPRDHR mirror registers [Memory Mapped]
    CMPAM 0x02F60000 Union of CMPA:CMPAHR mirror registers [Memory Mapped]
    DCTRIPSEL 0xAAAA Digital Compare Trip Select [Memory Mapped]
    DCACTL 0x0002 Digital Compare A Control [Memory Mapped]
    DCBCTL 0x0002 Digital Compare B Control [Memory Mapped]
    DCFCTL 0x0000 Digital Compare Filter Control [Memory Mapped]
    DCCAPCTL 0x0000 Digital Compare Capture Control [Memory Mapped]
    DCFOFFSET 0x0000 Digital Compare Filter Offset [Memory Mapped]
    DCFOFFSETCNT 0x0000 Digital Compare Filter Offset Counter [Memory Mapped]
    DCFWINDOW 0x0000 Digital Compare Filter Window [Memory Mapped]
    DCFWINDOWCNT 0x0000 Digital Compare Filter Window Counter [Memory Mapped]
    DCCAP 0x0000 Digital Compare Filter Counter Capture [Memory Mapped]
    ePWM3 ePWM3 Registers
    TBCTL 0x200A Time Base Control Register [Memory Mapped]
    TBSTS 0x0003 Time Base Status Register [Memory Mapped]
    TBPHS 0x00000000 Union of TBPHS:TBPHSHR [Memory Mapped]
    TBCTR 0x0379 Time Base Counter [Memory Mapped]
    TBPRD 0x0600 Time Base Period register set [Memory Mapped]
    TBPRDHR 0x0000 Time Base Period High Res Register [Memory Mapped]
    CMPCTL 0x0005 Compare control [Memory Mapped]
    CMPA 0x03000000 Union of CMPA:CMPAHR [Memory Mapped]
    CMPB 0x0000 Compare B reg [Memory Mapped]
    AQCTLA 0x0060 Action qual output A [Memory Mapped]
    AQCTLB 0x0060 Action qual output B [Memory Mapped]
    AQSFRC 0x0080 Action qual SW force [Memory Mapped]
    AQCSFRC 0x0000 Action qualifier continuous SW force [Memory Mapped]
    DBCTL 0x002B Dead-band control [Memory Mapped]
    DBRED 0x0022 Dead-band rising edge delay [Memory Mapped]
    DBFED 0x0022 Dead-band falling edge delay [Memory Mapped]
    TZSEL 0x0100 Trip zone select [Memory Mapped]
    TZDCSEL 0x0082 Trip zone digital comparator select [Memory Mapped]
    TZCTL 0x0226 Trip zone control [Memory Mapped]
    TZEINT 0x0000 Trip zone interrupt enable [Memory Mapped]
    TZFLG 0x0000 Trip zone interrupt flags [Memory Mapped]
    TZCLR 0x0000 Trip zone clear [Memory Mapped]
    TZFRC 0x0000 Trip zone force interrupt [Memory Mapped]
    ETSEL 0x0000 Event trigger selection [Memory Mapped]
    ETPS 0x0000 Event trigger pre-scaler [Memory Mapped]
    ETFLG 0x0000 Event trigger flags [Memory Mapped]
    ETCLR 0x0000 Event trigger clear [Memory Mapped]
    ETFRC 0x0000 Event trigger force [Memory Mapped]
    PCCTL 0x0000 PWM chopper control [Memory Mapped]
    HRCNFG 0x0000 HRPWM Config Reg [Memory Mapped]
    HRPCTL 0x0000 High Resolution Period Control [Memory Mapped]
    TBPRDM 0x06000000 Union of TBPRD:TBPRDHR mirror registers [Memory Mapped]
    CMPAM 0x03000000 Union of CMPA:CMPAHR mirror registers [Memory Mapped]
    DCTRIPSEL 0xAAAA Digital Compare Trip Select [Memory Mapped]
    DCACTL 0x0002 Digital Compare A Control [Memory Mapped]
    DCBCTL 0x0002 Digital Compare B Control [Memory Mapped]
    DCFCTL 0x0000 Digital Compare Filter Control [Memory Mapped]
    DCCAPCTL 0x0000 Digital Compare Capture Control [Memory Mapped]
    DCFOFFSET 0x0000 Digital Compare Filter Offset [Memory Mapped]
    DCFOFFSETCNT 0x0000 Digital Compare Filter Offset Counter [Memory Mapped]
    DCFWINDOW 0x0000 Digital Compare Filter Window [Memory Mapped]
    DCFWINDOWCNT 0x0000 Digital Compare Filter Window Counter [Memory Mapped]
    DCCAP 0x0000 Digital Compare Filter Counter Capture [Memory Mapped]
    ePWM4 ePWM4 Registers
    TBCTL 0x200A Time Base Control Register [Memory Mapped]
    TBSTS 0x0003 Time Base Status Register [Memory Mapped]
    TBPHS 0x00000000 Union of TBPHS:TBPHSHR [Memory Mapped]
    TBCTR 0x0379 Time Base Counter [Memory Mapped]
    TBPRD 0x0600 Time Base Period register set [Memory Mapped]
    TBPRDHR 0x0000 Time Base Period High Res Register [Memory Mapped]
    CMPCTL 0x0005 Compare control [Memory Mapped]
    CMPA 0x03000000 Union of CMPA:CMPAHR [Memory Mapped]
    CMPB 0x0000 Compare B reg [Memory Mapped]
    AQCTLA 0x0060 Action qual output A [Memory Mapped]
    AQCTLB 0x0060 Action qual output B [Memory Mapped]
    AQSFRC 0x0080 Action qual SW force [Memory Mapped]
    AQCSFRC 0x0009 Action qualifier continuous SW force [Memory Mapped]
    DBCTL 0x002B Dead-band control [Memory Mapped]
    DBRED 0x0022 Dead-band rising edge delay [Memory Mapped]
    DBFED 0x0022 Dead-band falling edge delay [Memory Mapped]
    TZSEL 0x0100 Trip zone select [Memory Mapped]
    TZDCSEL 0x0082 Trip zone digital comparator select [Memory Mapped]
    TZCTL 0x0226 Trip zone control [Memory Mapped]
    TZEINT 0x0000 Trip zone interrupt enable [Memory Mapped]
    TZFLG 0x0000 Trip zone interrupt flags [Memory Mapped]
    TZCLR 0x0000 Trip zone clear [Memory Mapped]
    TZFRC 0x0000 Trip zone force interrupt [Memory Mapped]
    ETSEL 0x0000 Event trigger selection [Memory Mapped]
    ETPS 0x0000 Event trigger pre-scaler [Memory Mapped]
    ETFLG 0x0000 Event trigger flags [Memory Mapped]
    ETCLR 0x0000 Event trigger clear [Memory Mapped]
    ETFRC 0x0000 Event trigger force [Memory Mapped]
    PCCTL 0x0000 PWM chopper control [Memory Mapped]
    HRCNFG 0x0000 HRPWM Config Reg [Memory Mapped]
    HRPCTL 0x0000 High Resolution Period Control [Memory Mapped]
    TBPRDM 0x06000000 Union of TBPRD:TBPRDHR mirror registers [Memory Mapped]
    CMPAM 0x03000000 Union of CMPA:CMPAHR mirror registers [Memory Mapped]
    DCTRIPSEL 0xAAAA Digital Compare Trip Select [Memory Mapped]
    DCACTL 0x0002 Digital Compare A Control [Memory Mapped]
    DCBCTL 0x0002 Digital Compare B Control [Memory Mapped]
    DCFCTL 0x0000 Digital Compare Filter Control [Memory Mapped]
    DCCAPCTL 0x0000 Digital Compare Capture Control [Memory Mapped]
    DCFOFFSET 0x0000 Digital Compare Filter Offset [Memory Mapped]
    DCFOFFSETCNT 0x0000 Digital Compare Filter Offset Counter [Memory Mapped]
    DCFWINDOW 0x0000 Digital Compare Filter Window [Memory Mapped]
    DCFWINDOWCNT 0x0000 Digital Compare Filter Window Counter [Memory Mapped]
    DCCAP 0x0000 Digital Compare Filter Counter Capture [Memory Mapped]
    ePWM5 ePWM5 Registers
    TBCTL 0x2006 Time Base Control Register [Memory Mapped]
    TBSTS 0x0003 Time Base Status Register [Memory Mapped]
    TBPHS 0x00000000 Union of TBPHS:TBPHSHR [Memory Mapped]
    TBCTR 0x0376 Time Base Counter [Memory Mapped]
    TBPRD 0x0600 Time Base Period register set [Memory Mapped]
    TBPRDHR 0x0000 Time Base Period High Res Register [Memory Mapped]
    CMPCTL 0x0000 Compare control [Memory Mapped]
    CMPA 0x00000000 Union of CMPA:CMPAHR [Memory Mapped]
    CMPB 0x0000 Compare B reg [Memory Mapped]
    AQCTLA 0x0000 Action qual output A [Memory Mapped]
    AQCTLB 0x0000 Action qual output B [Memory Mapped]
    AQSFRC 0x0000 Action qual SW force [Memory Mapped]
    AQCSFRC 0x0000 Action qualifier continuous SW force [Memory Mapped]
    DBCTL 0x0000 Dead-band control [Memory Mapped]
    DBRED 0x0000 Dead-band rising edge delay [Memory Mapped]
    DBFED 0x0000 Dead-band falling edge delay [Memory Mapped]
    TZSEL 0x0000 Trip zone select [Memory Mapped]
    TZDCSEL 0x0000 Trip zone digital comparator select [Memory Mapped]
    TZCTL 0x0000 Trip zone control [Memory Mapped]
    TZEINT 0x0000 Trip zone interrupt enable [Memory Mapped]
    TZFLG 0x0000 Trip zone interrupt flags [Memory Mapped]
    TZCLR 0x0000 Trip zone clear [Memory Mapped]
    TZFRC 0x0000 Trip zone force interrupt [Memory Mapped]
    ETSEL 0x000B Event trigger selection [Memory Mapped]
    ETPS 0x1101 Event trigger pre-scaler [Memory Mapped]
    ETFLG 0x0000 Event trigger flags [Memory Mapped]
    ETCLR 0x0000 Event trigger clear [Memory Mapped]
    ETFRC 0x0000 Event trigger force [Memory Mapped]
    PCCTL 0x0000 PWM chopper control [Memory Mapped]
    HRCNFG 0x0000 HRPWM Config Reg [Memory Mapped]
    HRPCTL 0x0000 High Resolution Period Control [Memory Mapped]
    TBPRDM 0x06000000 Union of TBPRD:TBPRDHR mirror registers [Memory Mapped]
    CMPAM 0x00000000 Union of CMPA:CMPAHR mirror registers [Memory Mapped]
    DCTRIPSEL 0x0000 Digital Compare Trip Select [Memory Mapped]
    DCACTL 0x0000 Digital Compare A Control [Memory Mapped]
    DCBCTL 0x0000 Digital Compare B Control [Memory Mapped]
    DCFCTL 0x0000 Digital Compare Filter Control [Memory Mapped]
    DCCAPCTL 0x0000 Digital Compare Capture Control [Memory Mapped]
    DCFOFFSET 0x0000 Digital Compare Filter Offset [Memory Mapped]
    DCFOFFSETCNT 0x0000 Digital Compare Filter Offset Counter [Memory Mapped]
    DCFWINDOW 0x0000 Digital Compare Filter Window [Memory Mapped]
    DCFWINDOWCNT 0x0000 Digital Compare Filter Window Counter [Memory Mapped]
    DCCAP 0x0000 Digital Compare Filter Counter Capture [Memory Mapped]
  • 0 in reply to Radey Shouman
    TI__Mastermind 42195 points
    Yes, that seems like it should work... I don't have a good reason why it wouldn't work.

    Can you try enabling phase loading for EPWM2 and then using the SWFSYNC?


    Regards,
    Cody
  • 0 in reply to Cody Watkins
    Prodigy 190 points
    I set the PHSEN bit in TBCTL for PWM1-4 (as well as PWM5). The result was the same: After writing 1 to TBCTL[SWFSYNC] for PWM2,
    TBSTS[SYNCI] was set for PWM3-5, indicating that a sync had been received, but TBPHS was not loaded for any of them.

    I have looked for examples of using SWFSYNC, do you know of any?

    regards,

    Radey
  • 0 in reply to Radey Shouman
    TI__Mastermind 42195 points
    Radey,
    Can you share a simple .out file that shows the problem?

    Thanks,
    Cody
  • 0 in reply to Cody Watkins
    Prodigy 190 points
    Cody,

    I would have to put one together, currently I only have a large application that I can't really post. It might take a few days for me to get to it.

    regards,

    Radey
  • 0 in reply to Radey Shouman
    TI__Mastermind 42195 points
    Radey,
    Often when trying to debug issues like this it can be helpful to strip down your code, please send it across if you complete it. In the meantime if I get a moment I will try to replicate it on my end.

    Regards,
    Cody
  • 0 in reply to Radey Shouman
    Prodigy 190 points

    pwm-test.zip, contains source code and .out file for a minimal test program, linked to run in flash.  PWM continues to misbehave as before.

    pwm-test.zip

  • 0 in reply to Cody Watkins
    Prodigy 190 points
    Hi Cody,

    I attached it one message upstream in a reply to myself -- not sure that you would notice that one.

    regards,

    Radey
  • 0 in reply to Radey Shouman
    TI__Mastermind 42195 points
    Radey,
    I see it, thanks! It will take me a a bit to get to it. I will try to get you a reply tomorrow.

    Regards,
    Cody
  • 0 in reply to Radey Shouman
    Prodigy 190 points
    Cody,

    Has there been any progress on this problem? We are getting ready to ship, and I would like to resolve this issue.

    regards,

    Radey
  • 0 in reply to Radey Shouman
    TI__Guru 62975 points
    Radey,

    Cody is currently out of the office on business travel. I was able to reproduce your behavior on my setup using some debug code based on your settings.

    After poking at my code, I found that the faulty phase load behavior on my setup was related to the placement of breakpoints (or ESTOP instructions) relative to the setting of the SWFSYNC bit. If I wait at least 6 CPU NOP cycles after setting the SWFSYNC bit before halting execution, the phase load executes as expected. If I do not add wait for 6 CPU NOP cycles, the SYNCI bit will be set, but the TBCTR will not be updated.

    The phase load works correctly without CPU NOP cycles when executing the code uninterrupted. It would seem that the interactive debug mechanisms are overly intrusive when it comes to the EPWM phase load functionality.

    Also, in case you are wanting to monitor the phase load and SYNCI status with software, I found that the EPWM registers require about 4 CPU NOP cycles to update with the new values after setting the SWFSYNC bit.

    Let us know if this helps.

    -Tommy
  • 0 in reply to tlee
    Prodigy 190 points

    Thanks, Tommy,

    What you say does seem to be the case, although I admit it doesn't give me enough of a warm fuzzy to undo my workaround.  I don't need CMPB for EPWM5 anyway.

    regards,

    Radey

  • 0 in reply to Radey Shouman
    TI__Guru 62975 points
    Radey,

    I'm glad that we were able to correlate.

    We were not aware of this issue before and will mark it for investigation.

    -Tommy