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TMS320F28069: CSI Tx interrupt question

farid mabr
Intellectual 810 points

Part Number: TMS320F28069

Hi,

I setup a SCI interrupt in my code as  below:

    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

    scia_fifo_init();  // Init SCI-A

void scia_fifo_init()
{
   SciaRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
                                  // No parity,8 char bits,
                                  // async mode, idle-line protocol
   SciaRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,
                                  // Disable RX ERR, SLEEP, TXWAKE
   SciaRegs.SCICTL2.bit.TXINTENA =1;
   SciaRegs.SCICTL2.bit.RXBKINTENA =1;
   SciaRegs.SCIHBAUD = 0x0000;
   SciaRegs.SCILBAUD = 0xC4; //14400
   SciaRegs.SCIFFTX.all=0xC022;
   SciaRegs.SCIFFRX.all=0x0022;
   SciaRegs.SCIFFCT.all=0x00;
   SciaRegs.SCICTL1.all =0x0023;     // Relinquish SCI from Reset
   SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
   SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

}

this is my ISR:

__interrupt void sciaRxFifoIsr(void)
{

    GpioDataRegs.GPBTOGGLE.bit.GPIO39=1;

    if(SciaRegs.SCIRXST.bit.RXERROR){
    SciaRegs.SCICTL1.bit.SWRESET=0; // Reset active low.
    SciaRegs.SCICTL1.bit.SWRESET=1;
    }

    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;   // Clear Overflow flag
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;   // Clear Interrupt flag

    PieCtrlRegs.PIEACK.all|=0x100;       // Issue PIE ack
}

I noticed that when I use my PC keyboard to send a character or a number ( from Terra Term), I have to hit the keyboard selected button twice in order to get an interrupt. I checked that in the debugger and also with the LED. the LED toggles only if I send the character twice.

Is that how this SCI interface work on this chip?

  • 0
    TI__Genius 17315 points
    Farid,

    Check the FIFO interrupt level bits.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 810 points
    Could you please give me more details: in what registers do I need to check for these FIFO bits?

    Thanks!
  • 0 in reply to farid mabr
    TI__Genius 17315 points
    Farid,

    Please refer to the F28069 TRM SCI chapter and see the FIFO registers:

    www.ti.com/lit/SPRUH18

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 810 points

    Hi Ken!

    Thank you for the update! in fact I tried to change my level bits at: 0-4 bits of the register SCIFFRX, but I did not see any change of the previous behavior I described earlier. However, when I commented out this line: //SciaRegs.SCIFFTX.all=0xC022; in my SCI setup fucnction(void scia_fifo_init()), I am able to get an interrupt after every character I send even though my FIFO level is set to 2: SciaRegs.SCIFFRX.all=0x0022; in fact it does not matter what value I put in 0-4 bits of SCIFFRX, always one character generates an interrupt. Not sure why SCIFFTX is affecting behavior of FIFO RX.

    Thanks,

    Farid

  • 0 in reply to farid mabr
    TI__Genius 17315 points
    Farid,

    To use the SCI FIFOs they must be enabled - SCIFFENA bit 14 in the SCIFFTX. When you included the line 'SciaRegs.SCIFFTX.all=0xC022;' the FIFO was enabled (for 2 words). By commenting out the line you disabled the FIFOs and hence received an interrupt for each character. In any case, it looks like you have it working now.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 810 points
    Thanks Ken for your reply. I am not talking anymore about SCIFFTX. I am having only a receive interrupt and it is setup as below:

    SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
    SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
    SciaRegs.SCICTL2.bit.TXINTENA =1;
    SciaRegs.SCICTL2.bit.RXBKINTENA =1;
    SciaRegs.SCIHBAUD = 0x0000;
    SciaRegs.SCILBAUD = SCI_PRD;
    SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
    SciaRegs.SCIFFRX.all=0x0022;
    SciaRegs.SCIFFCT.all=0x00;

    SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
    SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
    SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

    but iam not able to change the FIFO level anymore. I can receive only on Rx interrupt per word sent. what else do I need to change to get an interrupt after 2 characters received?
  • 0 in reply to farid mabr
    TI__Genius 17315 points
    Farid,

    Yes, I realize that you want an interrupt after receiving two words. From my previous post, you will need to enable - SCIFFENA bit 14 in the SCIFFTX. This enables the FIFOs for both transmit and receive. In the F2806x TRM see figure 13-10 on page 886 and notice that SCIFFENA controls both TX and RX FIFOs:

    www.ti.com/lit/SPRUH18

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 810 points
    I changed my code below so that I can received an interrupt after sending 4 characters, but I get an interrupt after I send only 2 chararcters> what am I missing here? Thanks!

    SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
    SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
    SciaRegs.SCICTL2.bit.TXINTENA =1;
    SciaRegs.SCICTL2.bit.RXBKINTENA =1;
    SciaRegs.SCIHBAUD = 0x0000;
    SciaRegs.SCILBAUD = 0xC4; //14400
    SciaRegs.SCIFFTX.all=0xC022;
    SciaRegs.SCIFFRX.all=0x0024;
    SciaRegs.SCIFFCT.all=0x00;

    SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
    SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
    SciaRegs.SCIFFRX.bit.RXFIFORESET=1;
  • 0 in reply to farid mabr
    TI__Genius 17315 points
    Farid,

    You have the TX FIFO set to generate an interrupt after sending 2 characters (not 4 characters), and the RX FIFO set to generate an interrupt after receiving 4 characters. Again, please see the TRM.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 810 points
    Something is still not right. I set Rx FIFO as above to generate an RX interrupt after sending 4 characters, that's right. I am not interested in TX interrupts. But I receive an RX interrupt after 2 characters are sent not 4. is there any other bits configuration I am missing here.

    even with this setup as below, i am not getting interrupts after 4 characters are sent:

    void scia_fifo_init()
    {
    SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
    SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
    SciaRegs.SCICTL2.bit.TXINTENA =1;
    SciaRegs.SCICTL2.bit.RXBKINTENA =1;
    SciaRegs.SCIHBAUD = 0x0000;
    SciaRegs.SCILBAUD = 0xC4; //14400
    SciaRegs.SCIFFTX.all=0xC024;
    SciaRegs.SCIFFRX.all=0x0024;
    SciaRegs.SCIFFCT.all=0x00;

    SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
    SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
    SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

    }
  • 0 in reply to farid mabr
    TI__Genius 17315 points
    Farid,

    Check to make sure the baud rates match. Also, try the communication at a slower baud rate to isolate any hardware issues.

    - Ken