Part Number: LAUNCHXL-F28379D
Hi All,
Im stuck when i am changing the CMPA vale of epwm . By changing the ADC value.
ADC will continue sample the signal using pwm 7 and that result im not able to feed to CMPA.
Below is the code.
Check the ADC ISR in which i have set CMPA value and its calculation When it reach 4095 the CMPA value get 100 but below that it is zero.
/* SYSTEM CLOCK = 200MHZ
* EPWM CLOCK = 200/2 = 100MHZ
*
* TBCLK = 100/(10*1) = 10MHZ
*
* TBPRD = (10M/16.66KHZ)*(1/2) = 300
*
* IN UP-DOWN FREQ. WILL BE HALF AS COPMARE TO UP/DOWN
*
* SO PERIOD IS 300. CMPA = 100 , CMPB = 200 , TPBRD = 300
*
* WE ARE USING 6-PWM PWM1 (PIN 40)-J4
* PWM2 (PIN 38)
* PWM3 (PIN 36)
*
* PWM4 (PIN 80)-J8
* PWM5 (PIN 78)
* PWM6 (PIN 76)
*
*
* IT IS SYMETRIC UP-DOWN MODE.
*
* WE CAN SET RED AND FED AS PER OUR REQ.
*
* */
#include "F28x_Project.h"
#include "My_PWM_Init.h"
#include "My_ADC_Init.h"
#include "My_ISR.h"
#include <math.h>
#define Stopped 0
#define ADC_BUF_LEN 50 // ADC buffer length
void motor_start(void);
void motor_stop(void);
void counter(void);
void start_adc_conv(void);
__interrupt void epwm1_isr(void);
__interrupt void epwm2_isr(void);
__interrupt void epwm3_isr(void);
__interrupt void epwm4_isr(void);
__interrupt void epwm5_isr(void);
__interrupt void epwm6_isr(void);
// Motor and Commutation Variables
unsigned int Desired_PWM_DutyCycle, Current_PWM_DutyCycle, PWM_BucketStep, PWM_Update_Counter, ADC_Sample_Counter;
unsigned char PreDriver_Sequence, Hall_IN, Motor_Status, Hall_State_Unknown;
unsigned char Motor_status;
// ADC Variables
unsigned long ADC_Results[4];
unsigned int Avg_vBUS, Avg_vPOT;
unsigned char SampleADC;
// Here We can define the RED FED max-min value
#define EPWM1_MAX_DB 1024
#define EPWM2_MAX_DB 1024
#define EPWM3_MAX_DB 0x64
#define EPWM4_MAX_DB 0x64
#define EPWM5_MAX_DB 0x64
#define EPWM6_MAX_DB 0x64
#define EPWM1_MIN_DB 0
#define EPWM2_MIN_DB 0
#define EPWM3_MIN_DB 0
#define EPWM4_MIN_DB 0
#define EPWM5_MIN_DB 0
#define EPWM6_MIN_DB 0
#define ADC_SAMPLE_PERIOD 1999 // ADC Sample period 50khz sampling rate
#define ADC_BUF_LEN 50 // ADC buffer length
Uint16 AdcBuf[ADC_BUF_LEN];
#define DB_UP 1
#define DB_DOWN 0
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
Uint32 EPwm4TimerIntCount;
Uint32 EPwm5TimerIntCount;
Uint32 EPwm6TimerIntCount;
Uint16 EPwm1_DB_Direction;
Uint16 EPwm2_DB_Direction;
Uint16 EPwm3_DB_Direction;
Uint16 EPwm4_DB_Direction;
Uint16 EPwm5_DB_Direction;
Uint16 EPwm6_DB_Direction;
//Uint16 data;
Uint16 CMPA_Val1;
Uint16 AdcaResults;
float32 data;
typedef struct
{
volatile struct EPWM_REGS *EPwmRegHandle;
Uint16 EPwm_CMPA_Direction;
Uint16 EPwm_CMPB_Direction;
Uint16 EPwmTimerIntCount;
Uint16 EPwmMaxCMPA;
Uint16 EPwmMinCMPA;
Uint16 EPwmMaxCMPB;
Uint16 EPwmMinCMPB;
}EPWM_INFO;
EPWM_INFO epwm1_info;
EPWM_INFO epwm2_info;
EPWM_INFO epwm3_info;
#define EPWM1_MAX_CMPA 300
#define EPWM1_MIN_CMPA 100
#define EPWM_CMP_UP 1
#define EPWM_CMP_DOWN 0
void update_compare(EPWM_INFO*);
void Clock_Enable_PWM1_7(void);
void Init_EPwm1_Gpio(void);
void Init_EPwm2_Gpio(void);
void Init_EPwm3_Gpio(void);
void Init_EPwm4_Gpio(void);
void Init_EPwm5_Gpio(void);
void Init_EPwm6_Gpio(void);
void Init_EPwm7_Gpio(void);
void InitEPwm1Example(void);
void InitEPwm3Example(void);
void InitEPwm2Example(void);
void InitEPwm5Example(void);
void InitEPwm4Example(void);
void InitEPwm6Example(void);
void InitEPwm7Example(void);
void InitAdca(void);
void main(void)
{
InitSysCtrl();
// Clock enable for epwm 1-6
Clock_Enable_PWM1_7();
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
Init_EPwm1_Gpio();
// Init_EPwm2_Gpio();
Init_EPwm3_Gpio();
Init_EPwm4_Gpio();
Init_EPwm5_Gpio();
Init_EPwm6_Gpio();
Init_EPwm7_Gpio();
// Disable CPU interrupts
DINT;
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.EPWM2_INT = &epwm2_isr;
PieVectTable.EPWM3_INT = &epwm3_isr;
PieVectTable.EPWM4_INT = &epwm4_isr;
PieVectTable.EPWM5_INT = &epwm5_isr;
PieVectTable.EPWM6_INT = &epwm6_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
// The TBCLKSYNC bit in the peripheral clock enable registers allows all users to globally synchronize all
// enabled ePWM modules to the time-base clock (TBCLK).
InitEPwm1Example();
// ADC Initialization
InitAdca();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1;
EDIS;
InitEPwm1Example();
InitEPwm3Example();
InitEPwm2Example();
InitEPwm5Example();
InitEPwm4Example();
InitEPwm6Example();
InitEPwm7Example(); /// ADC - EPWM SOC
//InitEPwm1Example();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// Initialize counters:
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
EPwm4TimerIntCount = 0;
EPwm5TimerIntCount = 0;
EPwm6TimerIntCount = 0;
// Enable CPU INT3 which is connected to EPWM1-3 INT:
IER |= M_INT3;
IER |= 0x0001; // Enable ADCA1 interrupt in PIE group 1*/
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
PieCtrlRegs.PIEIER3.bit.INTx4 = 1;
PieCtrlRegs.PIEIER3.bit.INTx5 = 1;
PieCtrlRegs.PIEIER3.bit.INTx6 = 1;
//--- Enable the ADC interrupt
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT1 in IER to enable PIE group -- ok
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//--- Enable global interrupts
asm(" CLRC INTM, DBGM"); // Enable global interrupts and realtime debug
for(;;)
{
asm (" NOP");
}
}
//Clock Enable PWM1/2...6
void Clock_Enable_PWM1_7(void)
{
CpuSysRegs.PCLKCR2.bit.EPWM1=1;
CpuSysRegs.PCLKCR2.bit.EPWM2=1;
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
CpuSysRegs.PCLKCR2.bit.EPWM4=1;
CpuSysRegs.PCLKCR2.bit.EPWM5=1;
CpuSysRegs.PCLKCR2.bit.EPWM6=1;
CpuSysRegs.PCLKCR2.bit.EPWM7=1; // ADC
}
// InitEPwm1Gpio - Initialize EPWM1 GPIOs
void Init_EPwm1_Gpio(void)
{
EALLOW;
// Disable internal pull-up for the selected output pins
// for reduced power consumption
// Pull-ups can be enabled or disabled by the user.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B)
// Configure EPWM-1 pins using GPIO regs
// This specifies which of the possible GPIO pins will be EPWM1 functional
// pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
EDIS;
}
// InitEPwm2Gpio - Initialize EPWM2 GPIOs
void Init_EPwm2_Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO1 (EPWM1B)
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO1 as EPWM1B
EDIS;
}
// InitEPwm3Gpio - Initialize EPWM3 GPIOs
void Init_EPwm3_Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A)
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B)
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
EDIS;
}
// InitEPwm4Gpio - Initialize EPWM4 GPIOs
void Init_EPwm4_Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A)
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B)
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
EDIS;
}
// InitEPwm5Gpio - Initialize EPWM5 GPIOs
void Init_EPwm5_Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A)
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B)
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
EDIS;
}
// InitEPwm6Gpio - Initialize EPWM6 GPIOs
void Init_EPwm6_Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A)
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B)
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
EDIS;
}
//------------------------------------------------------------------------------------------------------
// OK -- For PWM 1 (+)
void InitEPwm1Example()
{
//Uint16 CMPA_Val1;
EALLOW; // Enable EALLOW protected register access
DevCfgRegs.SOFTPRES2.bit.EPWM1 = 1; // ePWM1 is reset
DevCfgRegs.SOFTPRES2.bit.EPWM1 = 0; // ePWM1 is released from reset
EDIS;
//counter();
EPwm1Regs.TBPRD = 300; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x05; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 0x00;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
//CMPA_Val1 = (Uint16)AdcaResultRegs.ADCRESULT0;
//EPwm1Regs.CMPA.bit.CMPA = 100; // CMPA value -> 33.33% Duty Cycle
EPwm1Regs.AQCTLA.bit.PRD = AQ_SET; // Set on PRD
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear on CMPA down
// Active Low PWMs - Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED.bit.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED.bit.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing
// CMPA & CMPB
epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_UP;
epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter
epwm1_info.EPwmRegHandle = &EPwm1Regs; // Set the pointer to the
// ePWM module
epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA; // Setup min/max
// CMPA/CMPB values
epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA;
}
// OK -- For PWM 2 (-)
// OK FOR COMPLEMENT NEED TO iNTIALIZE PWM OUTSIDE TBSYNC
// InitEPwm2Example - Initialize EPWM2 configuration
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 300; // Set timer period
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0x05; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = 0x00; // Slow just to observe on
// Setup compare
EPwm2Regs.CMPA.bit.CMPA = 200;
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Clear PWM2 on Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2 on CMPA Up
// Active Low complementary PWMs - setup the deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED.bit.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED.bit.DBFED = EPWM2_MIN_DB;
EPwm2_DB_Direction = DB_UP;
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
// OK
// InitEPwm3Example - Initialize EPWM3 configuration
//
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 300; // Set timer period
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCL
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0x05; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = 0x00; // Slow so we can observe on
// Setup compare
EPwm3Regs.CMPA.bit.CMPA = 100;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
// Active high complementary PWMs - Setup the deadband
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED.bit.DBRED = EPWM3_MIN_DB;
EPwm3Regs.DBFED.bit.DBFED = EPWM3_MIN_DB;
EPwm3_DB_Direction = DB_UP;
// Interrupt where we will change the deadband
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
// OK
void InitEPwm4Example()
{
EPwm4Regs.TBPRD = 300; // Set timer period
EPwm4Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0x05; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = 0x00; // Slow so we can observe on
// Setup compare
EPwm4Regs.CMPA.bit.CMPA = 200;
// Set actions
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLA.bit.CAD = AQ_SET;
// Active high complementary PWMs - Setup the deadband
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm4Regs.DBRED.bit.DBRED = EPWM4_MIN_DB;
EPwm4Regs.DBFED.bit.DBFED = EPWM4_MIN_DB;
EPwm4_DB_Direction = DB_UP;
// Interrupt where we will change the deadband
EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm4Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm4Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
// OK
void InitEPwm5Example()
{
EPwm5Regs.TBPRD = 300; // Set timer period
EPwm5Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm5Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0x05; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = 0x00; // Slow so we can observe on
// Setup compare
EPwm5Regs.CMPA.bit.CMPA = 100;
// Set actions
EPwm5Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm5Regs.AQCTLA.bit.PRD = AQ_CLEAR;
// Active high complementary PWMs - Setup the deadband
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm5Regs.DBRED.bit.DBRED = EPWM5_MIN_DB;
EPwm5Regs.DBFED.bit.DBFED = EPWM5_MIN_DB;
EPwm5_DB_Direction = DB_UP;
// Interrupt where we will change the deadband
EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm5Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm5Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
// OK
void InitEPwm6Example()
{
EPwm6Regs.TBPRD = 300; // Set timer period
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0x05; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = 0x00; // Slow so we can observe on
// Setup compare
EPwm6Regs.CMPA.bit.CMPA = 200;
// Set actions
EPwm6Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm6Regs.AQCTLA.bit.ZRO = AQ_SET;
// Active high complementary PWMs - Setup the deadband
EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm6Regs.DBRED.bit.DBRED = EPWM6_MIN_DB;
EPwm6Regs.DBFED.bit.DBFED = EPWM6_MIN_DB;
EPwm6_DB_Direction = DB_UP;
// Interrupt where we will change the deadband
EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm6Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm6Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//-------------------------------------------------------------------------------------------------------
// Configure ePWM7 to trigger ADC SOCA at a 50 kHz rate
//-------------------------------------------------------------------------------------------------------
void Init_EPwm7_Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Disable pull-up on GPIO10 (EPWM6A)
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Disable pull-up on GPIO11 (EPWM6B)
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0; // Configure GPIO10 as EPWM6A
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0; // Configure GPIO11 as EPWM6B
EDIS;
}
void InitEPwm7Example(void)
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1;
EDIS;
EALLOW; // Enable EALLOW protected register access
DevCfgRegs.SOFTPRES2.bit.EPWM7 = 1; // ePWM7 is reset
DevCfgRegs.SOFTPRES2.bit.EPWM7 = 0; // ePWM7 is released from reset
EDIS; // Disable EALLOW protected register access
EPwm7Regs.TBCTL.bit.CTRMODE = 0x3; // Disable the timer
EPwm7Regs.TBCTL.all = 0xC033; // Configure timer control register
// bit 15-14 11: FREE/SOFT, 11 = ignore emulation suspend
// bit 5-4 11: SYNCOSEL, 11 = sync-out disabled
// bit 1-0 11: CTRMODE, 11 = timer stopped (disabled)
EPwm7Regs.TBCTR = 0x0000; // Clear timer counter
EPwm7Regs.TBPRD = ADC_SAMPLE_PERIOD; // Set timer period
EPwm7Regs.TBPHS.bit.TBPHS = 0x0000; // Set timer phase
EPwm7Regs.ETPS.all = 0x0100; // Configure SOCA
// bit 9-8 01: SOCAPRD, 01 = generate SOCA on first event
EPwm7Regs.ETSEL.all = 0x0A00; // Enable SOCA to ADC
// bit 11 1: SOCAEN, 1 = enable SOCA
// bit 10-8 010: SOCASEL, 010 = SOCA on PRD event
EPwm7Regs.TBCTL.bit.CTRMODE = 0x0; // Enable the timer in count up mode
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
//---------------------------------------------------------------------
//--- Enable the clocks to the ePWM module.
//--- Note: this should be done after all ePWM modules are configured
//--- to ensure synchronization between the ePWM modules.
//---------------------------------------------------------------------
}
void update_compare(EPWM_INFO *epwm_info)
{
/* // Every 10'th interrupt, change the CMPA/CMPB values
if( 0 < data && data < 300 )
{
epwm_info->EPwmTimerIntCount = 0;
// If we were increasing CMPA, check to see if
// we reached the max value. If not, increase CMPA
// else, change directions and decrease CMPA
if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP)
{
if(epwm_info->EPwmRegHandle->CMPA.bit.CMPA < epwm_info->EPwmMaxCMPA)
{
epwm_info->EPwmRegHandle->CMPA.bit.CMPA++;
}
else
{
epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN;
epwm_info->EPwmRegHandle->CMPA.bit.CMPA--;
}
}
//
// If we were decreasing CMPA, check to see if
// we reached the min value. If not, decrease CMPA
// else, change directions and increase CMPA
//
else
{
if(epwm_info->EPwmRegHandle->CMPA.bit.CMPA == epwm_info->EPwmMinCMPA)
{
epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP;
epwm_info->EPwmRegHandle->CMPA.bit.CMPA++;
}
else
{
epwm_info->EPwmRegHandle->CMPA.bit.CMPA--;
}
}
}
else
{
epwm_info->EPwmTimerIntCount++;
}
*/
}
__interrupt void epwm1_isr(void)
{
/*
if(EPwm1_DB_Direction == DB_UP)
{
if(EPwm1Regs.DBFED.bit.DBFED < EPWM1_MAX_DB)
{
EPwm1Regs.DBFED.bit.DBFED++;
EPwm1Regs.DBRED.bit.DBRED++;
}
else
{
EPwm1_DB_Direction = DB_DOWN;
EPwm1Regs.DBFED.bit.DBFED--;
EPwm1Regs.DBRED.bit.DBRED--;
}
}
else
{
if(EPwm1Regs.DBFED.bit.DBFED == EPWM1_MIN_DB)
{
EPwm1_DB_Direction = DB_UP;
EPwm1Regs.DBFED.bit.DBFED++;
EPwm1Regs.DBRED.bit.DBRED++;
}
else
{
EPwm1Regs.DBFED.bit.DBFED--;
EPwm1Regs.DBRED.bit.DBRED--;
}
}
*/
//EPwm1_DB_Direction = DB_UP;
//EPwm1Regs.DBRED.bit.DBRED = EPWM1_MAX_DB;
//EPwm1Regs.DBFED.bit.DBFED = 1;
update_compare(&epwm1_info);
EPwm1TimerIntCount++;
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void epwm2_isr(void)
{
//EPwm1_DB_Direction = DB_UP;
//EPwm1Regs.DBRED.bit.DBRED = EPWM1_MAX_DB;
EPwm2Regs.DBFED.bit.DBFED = EPWM1_MAX_DB;
EPwm2TimerIntCount++;
// Clear INT flag for this timer
EPwm2Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void epwm3_isr(void)
{
//EPwm1_DB_Direction = DB_UP;
//EPwm1Regs.DBRED.bit.DBRED = EPWM1_MAX_DB;
EPwm3Regs.DBFED.bit.DBFED = EPWM3_MAX_DB;
EPwm3TimerIntCount++;
// Clear INT flag for this timer
EPwm3Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void epwm4_isr(void)
{
//EPwm1_DB_Direction = DB_UP;
//EPwm1Regs.DBRED.bit.DBRED = EPWM1_MAX_DB;
EPwm4Regs.DBFED.bit.DBFED = EPWM4_MAX_DB;
EPwm4TimerIntCount++;
// Clear INT flag for this timer
EPwm4Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void epwm5_isr(void)
{
//EPwm1_DB_Direction = DB_UP;
//EPwm1Regs.DBRED.bit.DBRED = EPWM1_MAX_DB;
EPwm5Regs.DBFED.bit.DBFED = EPWM5_MAX_DB;
EPwm5TimerIntCount++;
// Clear INT flag for this timer
EPwm5Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void epwm6_isr(void)
{
//EPwm1_DB_Direction = DB_UP;
//EPwm1Regs.DBRED.bit.DBRED = EPWM1_MAX_DB;
EPwm6Regs.DBFED.bit.DBFED = EPWM6_MAX_DB;
EPwm6TimerIntCount++;
// Clear INT flag for this timer
EPwm6Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
void InitAdca(void)
{
asm(" EALLOW"); // Enable EALLOW protected register access
//--- Reset the ADC. This is good programming practice.
DevCfgRegs.SOFTPRES13.bit.ADC_A = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_A = 0; // ADC is released from reset
//--- Configure the ADC base registers
AdcaRegs.ADCCTL1.all = 0x0004; // Main ADC configuration
// bit 2 1:INTPULSEPOS, INT pulse generation, 0=start of conversion, 1=end of conversion
AdcaRegs.ADCCTL2.all = 0x0006; // ADC clock configuration
// bit 3-0 0110: PRESCALE, ADC clock prescaler.
// 0110=CPUCLK/4
AdcaRegs.ADCBURSTCTL.all = 0x0000;
//--- Call AdcSetMode() to configure the resolution and signal mode.
// This also performs the correct ADC calibration for the configured mode.
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//--- SOC0 configuration
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 0x11; // Trigger -- epwm7 SOC
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // Convert channel -- 0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19; // Acquisition window -- 20
AdcaRegs.ADCINTSOCSEL1.bit.SOC0 = 0; // ADC interrupt triggers
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // SOC priority mode
//--- ADCA1 interrupt configuration
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Interrupt pulses 1 ADCINT1 pulses are generated whenever an EOC pulse
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // ADC interrupt enable
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // EOC triggers the interrupt ??
//--- Enable the ADC interrupt
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT1 in IER to enable PIE group -- ok
IER |= 0x0001; // Enable ADCA1 interrupt in PIE group 1
//--- Finish up
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC
DELAY_US(1000); // Wait 1 ms after power-up before using the ADC
asm(" EDIS"); // Disable EALLOW protected register access
} // end InitAdc()
interrupt void ADCA1_ISR(void)
{
static Uint16 *AdcBufPtr = AdcBuf; // Pointer to buffer
static volatile Uint16 GPIO34_count = 0; // Counter for pin toggle
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Must acknowledge the PIE group
//--- Manage the ADC registers
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear ADCINT1 flag
//--- Read the ADC result
*AdcBufPtr++ = AdcaResultRegs.ADCRESULT0; // Read the result
//CMPA_Val1 = AdcaResultRegs.ADCRESULT0;
data = ((AdcaResultRegs.ADCRESULT0)/4095); <------- HERE im not able to change the cmpa value. When it reach 4095 the CMPA value get 100 but below that it is zero.
CMPA_Val1 = (Uint16)data;
EPwm1Regs.CMPA.bit.CMPA = CMPA_Val1;
/* if(0 < data && data <= 300 )
{
epwm1_info.EPwmRegHandle->CMPA.bit.CMPA = data;
}
*/
//--- Brute-force the circular buffer
/*if( AdcBufPtr == (AdcBuf + ADC_BUF_LEN) )
{
AdcBufPtr = AdcBuf; // Rewind the pointer to beginning
}
*/
}
