TMS320F2808: GPIO0 output glitch during power on

Cai,
I don't believe what you're seeing is a glitch, GPIO0 is simply driving high the entire time. So since it is driving high it will "output" whatever voltage is applied to the VDDIO pins.

To me, It looks like your power supply is overshooting on power up. Have you looked into your power supply?

Regards,
Cody

Hi Cody,

Yes, i have change the power supply and now it looks like this:

CH1 = GPIO0 ; CH2 = 3.3V,  CH3 = 1.9V, CH4 = /RESET

Any comments about this?

Thanks.

Cai

Hello Cai,

A few comments here:
1. On reset, the GPIO0 -GPIO11 pins internal pullups are not enabled. This means that there is a pullup on your board on GPIO0 tied to 3.3V. (explaining your original conditions) see Footnote #1 on the Signal Descriptions table in the datasheet: http://www.ti.com/lit/sprs230
2. Your reset line is not good here. It should be held low until the power is good. It looks like there is a very sloppy rise. Are you using an external SVS device to control/monitor POR/BOR? not only that, but it appears the RESET line is approaching 5 V???? Please make sure this is not the case. Are you sure you are scoping the XRSn signal and not an application Reset line?


Generally, please refer to the Power Sequencing section of the datasheet (http://www.ti.com/lit/sprs230) and ensure that you are following all of the recommendations there.

Thanks,
Mark

Mark,

Yes, we solve this issue and the problem is from reset pin.
Thanks.

If you don't mind, can you expand on what the issue was? This is more for my curiosity. Was it poor control of the XRSn pin of the MCU during power up?

Mark,

Yes, the RC value in the XRSn pin is not reasonable, which make the CPU in unknow status during power on.

Thanks for confirming that was the cause of your issue.

-Mark