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TMS320F28335: Clearing a RMP bit clears all other lower priority RMP reception mailbox bits in CAN

Part Number: TMS320F28335

Hi,

I am using the experimenters kit to use CAN in self test mode. I have configured 6 transmit mailboxes (MB10-MB15) and 6 receive mailboxes (MB26-MB31) in eCAN mode and 11-bit identifier. I am also displaying this data on the terminal over SCI when the data is read (within the interrupt).

    /*CAN0 Rx/Tx Interrupt Function*/
    interrupt void ecan0intA_isr(void)
    {
        //
        // Data variables for transmission receive unsigned, signed (for BDC)
        //
        unsigned int mailbox_nr, u_data;
        int s_data;
        char d;

        mailbox_nr = ECanaRegs.CANGIF0.bit.MIV0;    //mailbox that set GMIF0-I0EN


        ECanaShadow.CANTA.all = 0;

        //ECanaShadow.CANTRS.all = 0;

        //ECanaShadow.CANTRS.all = ECanaRegs.CANTRS.all;

         switch(mailbox_nr)
        {
           case(30):  // if mailbox #30 receive message
            {
                // and prepare MBX1 for next receive
                ECanaRegs.CANRMP.bit.RMP30 = 1;      // clear the status flag RMP1

                u_data = ECanaMboxes.MBOX30.MDH.byte.BYTE5;

                switch(u_data)
                {
                    case (0x20):
                            d = 'P';
                            break;
                    case (0x21):
                            d = 'R';
                            break;
                    case (0x22):
                            d = 'N';
                            break;
                    case (0x23):
                            d = 'D';
                            break;
                    default:
                            d = 'D';

                }



                //
                // load data
                //
                sprintf(str, "Drive mode is %c  \n", d);
                msg = str;
                scia_msg(msg);
                break;
            }

}

I am using interrupts to access the data. It works for the most part except when my RMP register is filled due to reception due to multiple mailboxes. In this case, the control goes the the highest priority (MB30 in this case). When I set the RMP bit to clear BIT30, the other bits are cleared as well and I lose the data from those MBs.

Is there something I am doing wrong? What can I do it fix this?

Thank you.

  • You need to use 32-bit access for R/W operations. This is done by using the shadow registers as shown in my app.note SPRA876. You are not employing 32-bit R/W below:
     
    mailbox_nr = ECanaRegs.CANGIF0.bit.MIV0;    //mailbox that set GMIF0-I0EN
     
     ECanaRegs.CANRMP.bit.RMP30 = 1;      // clear the status flag RMP1
     
    If you  access bit-fields directly like this, the results could be unpredictable. Specifically, for CANRMP, a set RMP bit is cleared by writing a 1 to it. If a write is corrupted, it could inadvertently clear other set RMP bits, which is perhaps what you are seeing. Please refer to CAN_RXINT_A project in my app.note, which shows the correct way of clearing the RMP bit.
  • Thanks a lot for that Hareesh! That fixed it :)