Dear experts:
When I configure the BIT region of "TBPRDLINK" and "CMPALINK" and "CMPALINK" in REGISTER "EPWMXLINK" in "EPWM 2 MODULE" to be linked to EPWM2. I find that it does not work. The code is as the followwing.
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/*EPWM Module 2 config to LLC Pri 2 driver */
/************************************/
EPwm2Regs.EPWMXLINK.bit.TBPRDLINK = 0;
EPwm2Regs.EPWMXLINK.bit.CMPALINK = 0;
EPwm2Regs.EPWMXLINK.bit.CMPBLINK = 0;
EPwm2Regs.GLDCTL.bit.GLD=1;
EPwm2Regs.GLDCTL.bit.OSHTMODE=0x00;
EPwm2Regs.GLDCTL.bit.GLDPRD=0X00;
EPwm2Regs.GLDCTL.bit.GLDMODE=0x03;
EPwm2Regs.GLDCFG.bit.TBPRD_TBPRDHR=1;
EPwm2Regs.GLDCFG.bit.DBRED_DBREDHR=1;
EPwm2Regs.GLDCFG.bit.DBFED_DBFEDHR=1;
EPwm2Regs.GLDCFG.bit.DBCTL=1;
EPwm2Regs.GLDCFG.bit.CMPA_CMPAHR=1;
EPwm2Regs.GLDCFG.bit.CMPB_CMPBHR=1;
EPwm2Regs.GLDCFG.bit.CMPC=1;
EPwm2Regs.GLDCFG.bit.CMPD=1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; /* Set Shadow load */
EPwm2Regs.TBCTL2.bit.PRDLDSYNC = 01; /*？TBCTR=0 SYNC OCCURSmust add sync point for load if need large delay*/
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; /*? Count-up mode */
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Enable phase loading */
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; /* Sync Output Select: TB_SYNC_IN */
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; /* TBCLK = EPWMCLK / (HSPCLKDIV x CLKDIV) */
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; /* = 100MHz / (1*1) = 100MHz */
EPwm2Regs.TBCTL.bit.PHSDIR=0;
EPwm2Regs.TBPRD = LLC_PWM_PER_DFT; /* PWM frequency = 60kHz */
EPwm2Regs.CMPA.bit.CMPA = LLC_PWM_DUTY_DFT; /* Set PWM duty as 50% */
EPwm2Regs.CMPB.bit.CMPB = LLC_PWM_DUTY_DFT; //0;
EPwm2Regs.TBPHS.bit.TBPHS = 00; /* Set as slave, phase = 0 */
EPwm2Regs.TBCTR = 0; /* Time base counter =0 */
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; /* Load on CTR=PRD */
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; /* Load on CTR=PRD */
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; /* Shadow mode. Operates as a double buffer. */
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; /* Shadow mode. Operates as a double buffer. */
EPwm2Regs.CMPCTL.bit.LOADASYNC=1;/**/
EPwm2Regs.CMPCTL.bit.LOADBSYNC=1;
//EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; /* Set PWM2A on Zero */
//EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; /* Clear PWM2A on event A, up count */
// EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; /* Set PWM2B on Zero */
// EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; /* Clear PWM2Bs on event B, up count */
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; /* Set PWM1A on Zero */
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; /* Clear PWM1A on event A, up count */
//EPwm2Regs.AQCTLA.bit.PRD =AQ_CLEAR;
//EPwm2Regs.AQCTLA.bit.CAD =AQ_SET;
EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; /* Set PWM1B on Zero */
// EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; /* Clear PWM1B on event B, up count */
//EPwm2Regs.AQCTLB.bit.PRD =AQ_SET;
EPwm2Regs.AQCTLB.bit.CAD =AQ_CLEAR;
EPwm2Regs.AQSFRC.bit.RLDCSF = 3; /* When software Force event come,Load immediately */
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED; /* EPWMxA is the source for both delays */
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; /* Enable Dead-band module */
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; /* Active High Complementary (AHC) */
// EPwm2Regs.DBCTL.bit.OUTSWAP = 3; /*swap output AQA-EPWMB*/
EPwm2Regs.DBCTL.bit.SHDWDBREDMODE = 1; /*enable shadow mode of DB*/
EPwm2Regs.DBCTL.bit.LOADREDMODE = 1; /*load shadow on prd*/
EPwm2Regs.DBCTL.bit.SHDWDBFEDMODE = 1; /*enable shadow mode of DB*/
EPwm2Regs.DBCTL.bit.LOADFEDMODE = 1; /*load shadow on prd*/
EPwm2Regs.DBRED.bit.DBRED = LLC_INIT_DEADBAND; /* RED = 30 TBCLKs initially */
EPwm2Regs.DBFED.bit.DBFED = LLC_INIT_DEADBAND; /* FED = 30 TBCLKs initially */
EPwm2Regs.AQCSFRC.bit.CSFA = 00; /* Disable EPWM2B output */
EPwm2Regs.AQCSFRC.bit.CSFB =00; /* Disable EPWM2A output */
